MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 137
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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Phase-Locked Loop (PLL)
3-clock
MOTOROLA
INT ECLK
CANCLK
T1CLK
T2CLK
T3CLK
T4CLK
PCLK
XCLK
The phase-locked loop (PLL) of the 68HC912D60A is designed for
robust operation in an Automotive environment. The proposed PLL
crystal or ceramic resonator reference of 0.5 to 8MHz is selected for the
wide availability of components with good stability in the desired
temperature range. Please refer to
Chains
An oscillator design with reduced power consumption allows for slow
wait operation with a typical power supply current lower than a
milli-ampere. The PLL circuitry can be bypassed when the VDDPLL
supply is at VSS level. In this case the oscillator output transistor has a
stronger transconductance, for a crystal at twice the bus frequency.
Refer to
Figure 13 Internal Clock Relationships
for an overview of system clocks.
Figure 7
Clock Functions
in
Pinout and Signal
Figure 18
Descriptions.
in section
MC68HC912DT128A Rev 2.0
Phase-Locked Loop (PLL)
Clock Divider
Clock Functions
137
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