MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 164
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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Real-Time Interrupt
Clock Monitor
Clock Functions
MC68HC912DT128A Rev 2.0
164
In addition, windowed COP operation can be selected. In this mode,
writes to the COPRST register must occur in the last 25% of the selected
period. A premature write will also reset the part.
There is a real time (periodic) interrupt available to the user. This
interrupt will occur at one of seven selected rates. An interrupt flag and
an interrupt enable bit are associated with this function. There are three
bits for the rate select.
The clock monitor circuit is based on an internal resistor-capacitor (RC)
time delay. If no EXTALi clock edges are detected within this RC time
delay, the clock monitor can optionally generate a system reset. The
clock monitor function is enabled/disabled by the CME control bit in the
COPCTL register. This time-out is based on an RC delay so that the
clock monitor can operate without any EXTALi clock.
Clock monitor time-outs are shown in
EXTALi clock period with an ideal 50% duty cycle is twice this time-out
value.
5 V +/– 10%
Table 25 Clock Monitor Time-Outs
Clock Functions
Supply
Table
25. The corresponding
2–20 S
Range
MOTOROLA
30-clock
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