MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 199
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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TSCR — Timer System Control Register
TCNT — Timer Count Register
13-ect
MOTOROLA
RESET:
RESET:
Bit 15
Bit 7
TEN
Bit 7
Bit 7
0
0
TSWAI
14
6
0
6
6
0
When the OC7Mn bit is set, a successful OC7 action will override a
successful OC[6:0] compare action during the same cycle; therefore, the
OCn action taken will depend on the corresponding OC7D bit.
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in
special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may be a
different size because the write is not synchronized with the prescaler
clock.
Read or write anytime.
TEN — Timer Enable
If for any reason the timer is not active, there is no 64 clock for the
pulse accumulator since the E 64 is generated by the timer prescaler.
0 = Disables the main timer, including the counter. Can be used for
1 = Allows the timer to function normally.
TSBCK
13
5
5
0
5
0
reducing power consumption.
Enhanced Capture Timer
TFFCA
12
4
4
0
4
0
11
3
3
0
3
0
10
2
2
0
2
0
MC68HC912DT128A Rev 2.0
1
9
1
0
1
0
Timer Register Descriptions
Enhanced Capture Timer
Bit 0
Bit 8
Bit 0
Bit 0
0
0
$0084–$0085
$0086
199
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