MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 213
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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DLYCT — Delay Counter Control Register
ICOVW — Input Control Overwrite Register
27-ect
MOTOROLA
RESET:
RESET:
NOVW7
BIT 7
BIT 7
0
0
0
NOVW6
6
0
0
6
0
PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable
Read or write any time.
If enabled, after detection of a valid edge on input capture pin, the delay
counter counts the pre-selected number of M clock (module clock)
cycles, then it will generate a pulse on its output. The pulse is generated
only if the level of input signal, after the preset delay, is the opposite of
the level before the transition.This will avoid reaction to narrow input
pulses.
After counting, the counter will be cleared automatically.
Delay between two active edges of the input signal period should be
longer than the selected counter delay.
DLYx — Delay Counter Select
Read or write any time.
0 = 8-Bit Pulse Accumulator is disabled.
1 = 8-Bit Pulse Accumulator is enabled.
NOVW5
5
0
0
5
0
Enhanced Capture Timer
NOVW4
4
0
0
4
0
DLY1
0
0
1
1
NOVW3
3
0
0
3
0
DLY0
0
1
0
1
NOVW2
Delay
Disabled (bypassed)
256M clock cycles
512M clock cycles
1024 M clock cycles
2
0
0
2
0
NOVW1
DLY1
MC68HC912DT128A Rev 2.0
1
0
1
0
Timer Register Descriptions
Enhanced Capture Timer
NOVW0
BIT 0
DLY0
BIT 0
0
0
$00AA
$00A9
213
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