MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 198
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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OC7D — Output Compare 7 Data Register
OC7M — Output Compare 7 Mask Register
Enhanced Capture Timer
MC68HC912DT128A Rev 2.0
198
RESET:
RESET:
OC7M7
OC7D7
Bit 7
Bit 7
NOTE:
0
0
OC7M6
OC7D6
6
0
6
0
FOC[7:0] — Force Output Compare Action for Channel 7-0
Read or write anytime.
The bits of OC7M correspond bit-for-bit with the bits of timer port
(PORTT). Setting the OC7Mn will set the corresponding port to be an
output port regardless of the state of the DDRTn bit when the
corresponding TIOSn bit is set to be an output compare. This does not
change the state of the DDRT bits. At successful OC7, for eachbit that
is set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
OC7M has priority over output action on timer port enabled by OMn and
OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the
action of corresponding OM and OL bits on the selected timer port.
Read or write anytime.
The bits of OC7D correspond bit-for-bit with the bits of timer port
(PORTT). When a successful OC7 compare occurs, for each bit that is
set in OC7M, the corresponding data bit in OC7D is stored to the
corresponding bit of the timer port.
A write to this register with the corresponding data bit(s) set causes
the action which is programmed for output compare “n” to occur
immediately. The action taken is the same as if a successful
comparison had just taken place with the TCn register except the
interrupt flag does not get set.
OC7M5
OC7D5
5
0
5
0
Enhanced Capture Timer
OC7M4
OC7D4
4
0
4
0
OC7M3
OC7D3
3
0
3
0
OC7M2
OC7D2
2
0
2
0
OC7M1
OC7D1
1
0
1
0
OC7M0
OC7D0
Bit 0
Bit 0
0
0
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