MC68HC912DG128A MOTOROLA [Motorola, Inc], MC68HC912DG128A Datasheet - Page 307
MC68HC912DG128A
Manufacturer Part Number
MC68HC912DG128A
Description
microcontroller unit 16BIT DEVICE
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC912DG128A.pdf
(404 pages)
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msCAN12
Identifier
Acceptance
Registers
(CIDAR0–7)
39-mscan12
MOTOROLA
CIDAR0
CIDAR1
CIDAR2
CIDAR3
CIDAR4
CIDAR5
CIDAR6
CIDAR7
$011A
$011B
$0118
$0119
$0110
$0112
$0113
$0111
RESET
RESET
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
Bit 7
Bit 7
AC7
AC7
AC7
AC7
AC7
AC7
AC7
AC7
-
-
Figure 55 Identifier Acceptance Registers (2nd bank)
Figure 54 Identifier Acceptance Registers (1st bank)
On reception each message is written into the background receive
buffer. The CPU is only signalled to read the message however, if it
passes the criteria in the identifier acceptance and identifier mask
registers (accepted); otherwise, the message will be overwritten by the
next message (dropped).
The acceptance registers of the msCAN12 are applied on the IDR0 to
IDR3 registers of incoming messages in a bit by bit manner.
For extended identifiers all four acceptance and mask registers are
applied. For standard identifiers only the first two (CIDMR0/1 and
CIDAR0/1) are applied. In the latter case it is required to program the
three last bits (AM2 – AM0) in the mask register CIDMR1 to ‘don’t care’.
AC6
AC6
AC6
AC6
AC6
AC6
AC6
AC6
6
6
-
-
AC5
AC5
AC5
AC5
AC5
AC5
AC5
AC5
5
5
-
-
MSCAN Controller
AC4
AC4
AC4
AC4
AC4
AC4
AC4
AC4
4
4
-
-
AC3
AC3
AC3
AC3
AC3
AC3
AC3
AC3
3
3
-
-
Programmer’s Model of Control Registers
AC2
AC2
AC2
AC2
AC2
AC2
AC2
AC2
2
2
-
-
MC68HC912DT128A Rev 2.0
AC1
AC1
AC1
AC1
AC1
AC1
AC1
AC1
1
1
-
-
MSCAN Controller
Bit 0
AC0
AC0
AC0
AC0
Bit 0
AC0
AC0
AC0
AC0
-
-
307
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