NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 13

• Manufacturer Part Number: NAND02GW3B2CN1F
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND01G-B2B, NAND02G-B2C
2
2.1
Memory array organization
The memory array is made up of NAND structures where 32 cells are connected in series.
The memory array is organized in blocks where each block contains 64 pages. The array is
split into two areas, the main area and the spare area. The main area of the array is used to
store data whereas the spare area is typically used to store Error correction Codes, software
flags or Bad Block identification.
In x8 devices the pages are split into a 2048 Byte main area and a spare area of 64 Bytes.
In the x16 devices the pages are split into a 1,024 Word main area and a 32 Word spare
area. Refer to
Bad blocks
The NAND Flash 2112 Byte/ 1056 Word Page devices may contain Bad Blocks, that is
blocks that contain one or more invalid bits whose reliability is not guaranteed. Additional
Bad Blocks may develop during the lifetime of the device.
The Bad Block Information is written prior to shipping (refer to
Management
Table 4: Valid Blocks
shown include both the Bad Blocks that are present when the device is shipped and the Bad
Blocks that could develop later on.
These blocks need to be managed using Bad Blocks Management, Block Replacement or
Error Correction Codes (refer to
Table 4.
Density of Device
Valid Blocks
for more details).
Figure 5: Memory Array
2 Gbits
1 Gbit
shows the minimum number of valid blocks in each device. The values
Section 8: Software
Organization.
2008
1004
Min
algorithms).
Section 8.1: Bad Block
Memory array organization
2048
1024
Max
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