NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 24

• Manufacturer Part Number: NAND02GW3B2CN1F
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Device operations
6.2
Figure 8.
24/62
RB
R
I/O
Setup
Read
Code
Cache Read
The Cache Read operation is used to improve the read throughput by reading data using
the Cache Register. As soon as the user starts to read one page, the device automatically
loads the next page into the Cache Register.
An Cache Read operation consists of three steps (see
1.
2.
3.
The Start Address must be at the beginning of a page (Column Address = 00h, see
and
see
The Ready/Busy signal can be used to monitor the start of the operation. During the latency
period the Ready/Busy signal goes Low, after this the Ready/Busy signal goes High, even if
the device is internally downloading page n+1.
Once the Cache Read operation has started, the Status Register can be read using the
Read Status Register command.
During the operation, SR5 can be read, to find out whether the internal reading is ongoing
(SR5 = ‘0’), or has completed (SR5 = ‘1’), while SR6 indicates whether the Cache Register
is ready to download new data.
To exit the Cache Read operation an Exit Cache Read command must be issued (see
Table
If the Exit Cache Read command is issued while the device is internally reading page n+1,
pages n and n+1 will not be output.
Cache Read Operation
00h
Figure 8
Table
One bus cycle is required to setup the Cache Read command (the same as the
standard Read command)
Four or Five (refer to
Start Address
One bus cycle is required to issue the Cache Read confirm command to start the P/E/R
Controller.
10).
Address
Inputs
9). This allows the data to be output uninterrupted after the latency time (t
(Read Busy time)
tBLBH1
Confirm
Cache
Read
Code
31h
Busy
Table 6
tRHRL2
1st page
and
Table
2nd page
7) bus cycles are then required to input the
Block N
3rd page
tRHRL2
Data Output
Table 10:
NAND01G-B2B, NAND02G-B2C
last page
Commands):
Cache
Read
Code
Exit
34h
tBLBH4
ai13104
Table 8
BLBH1
),