NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 18

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NAND02GW3B2CN1F

Manufacturer Part Number
NAND02GW3B2CN1F
Description
1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
Bus operations
4.5
4.6
18/62
Write Protect
Write Protect bus operations are used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or erase
operations and so the contents of the memory array cannot be altered. The Write Protect
signal is not latched by Write Enable to ensure protection even during power-up.
Standby
When Chip Enable is High the memory enters Standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 5.
1. Only for x16 devices.
2. WP must be V
Table 6.
1. Any additional address input cycles will be ignored.
2. The fifth cycle is valid for 2Gb devices. A28 is for 2Gb devices only.
Bus Cycle
Command Input
Bus Operation
Address Input
Write Protect
Data Output
Data Input
5
Standby
2
3
1
4
th(2)
nd
st
rd
th
(1)
Bus Operations
Address Insertion, x8 Devices
IH
I/O7
A19
A27
V
V
A7
when issuing a program or erase command.
IL
IL
V
V
V
V
V
E
X
IH
IL
IL
IL
IL
I/O6
A18
A26
V
AL
V
V
V
V
V
A6
X
X
IH
IL
IL
IL
IL
IL
V
CL
V
V
V
X
X
IH
IL
IL
IL
I/O5
A17
A25
V
V
A5
IL
IL
Fallin
V
V
V
R
X
X
g
IH
IH
IH
I/O4
A16
A24
V
V
A4
Rising
Rising
Rising
IL
IL
V
W
X
X
IH
V
I/O3
WP
X
A11
A15
A23
IL
V
V
V
A3
X
X
D
(2)
IH
/V
IL
IL
NAND01G-B2B, NAND02G-B2C
D
Data Output
I/O0 - I/O7
Command
Data Input
Address
I/O2
A10
A14
A22
V
A2
IL
X
X
I/O1
A13
A21
V
A1
A9
IL
I/O8 - I/O15
Data Output
Data Input
X
X
X
X
I/O0
A12
A20
A28
A0
A8
(1)

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