NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 7

• Manufacturer Part Number: NAND02GW3B2CN1F
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

NAND01G-B2B, NAND02G-B2C
1
Description
ST NAND01G-B2B and NAND02G-B2C Flash 2112 Byte/ 1056 Word Page is a family of
non-volatile Flash memories that uses NAND cell technology. The devices range from 1 Gbit
to 2 Gbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either
2112 Bytes (2048 + 64 spare) or 1056 Words (1024 + 32 spare) depending on whether the
device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or
x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of
NAND Flash devices it is strongly recommended to implement an Error Correction Code
(ECC).
The devices feature a Write Protect pin that allows performing hardware protection against
program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the
Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output
allows the Ready/Busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back Program command is available to optimize the management of defective
blocks. When a Page Program operation fails, the data can be programmed in another page
without having to resend the data to be programmed.
Each device has Cache Program and Cache Read features which improve the program and
read throughputs for large files. During Cache Programming, the device loads the data in a
Cache Register while the previous data is transferred to the Page Buffer and programmed
into the memory array. During Cache Reading, the device loads the data in a Cache
Register while the previous data is transferred to the I/O Buffers to be read.
All devices have the Chip Enable Don’t Care feature, which allows code to be directly
downloaded by a microcontroller, as Chip Enable transitions during the latency time do not
stop the read operation.
All devices have the option of a Unique Identifier (serial number), which allows each device
to be uniquely identified.
The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not
described in the datasheet. For more details of this option contact your nearest ST Sales
office.
The devices are available in the following packages:
In order to meet environmental requirements, ST offers the NAND01G-B2B and NAND02G-
B2C in ECOPACK
Level Interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label. ECOPACK is an ST trademark.
TSOP48 (12 x 20mm)
VFBGA63 (9.5 x 12 x 1mm, 0.8mm pitch) for NAND02G-B2C devices.
VFBGA63 (9 x 11 x 1mm, 0.8mm pitch) for NAND01G-B2B devices.
®
packages. ECOPACK packages are Lead-free. The category of second
Description
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