NAND02GW3B2CN1F STMICROELECTRONICS [STMicroelectronics], NAND02GW3B2CN1F Datasheet - Page 20

• Manufacturer Part Number: NAND02GW3B2CN1F
• Description: 1 Gbit, 2 Gbit, 2112 Byte/1056 Word Page, 1.8V/3V, NAND Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Command Set
5
20/62
Command Set
All bus write operations to the device are interpreted by the Command Interface. The
Commands are input on I/O0-I/O7 and are latched on the rising edge of Write Enable when
the Command Latch Enable signal is high. Device operations are selected by writing
specific commands to the Command Register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The Commands are summarized in
Table 10.
1. The bus cycles are only shown for issuing the codes. The cycles required to input the
2. Only during Cache Read busy.
Read
Random Data Output
Cache Read
Exit Cache Read
Page Program
(Sequential Input default)
Random Data Input
Copy Back Program
Cache Program
Block Erase
Reset
Read Electronic Signature
Read Status Register
addresses or input/output data are not shown.
Command
Commands
1
st
CYCLE 2
FFh
00h
05h
00h
34h
80h
85h
00h
80h
60h
90h
70h
Table 10:
Bus Write Operations
nd
Commands.
D0h
E0h
30h
31h
10h
35h
15h
CYCLE 3
–
–
–
–
–
rd
NAND01G-B2B, NAND02G-B2C
CYCLE 4
85h
–
–
–
–
–
–
–
–
–
–
–
(1)
th
CYCLE
10h
–
–
–
–
–
–
–
–
–
–
–
Commands
accepted
during
Yes
busy
Yes
Yes
(2)