HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 47

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

Table 21
1) 0 °C ≤ T
2) All parameters assumes proper device initialization.
3) AC timing tests measured at 0.9 V.
4) The transition time is measured between V
5) Specified t
6) If t
7) If t
8) These parameter account for the number of clock cycles and depend on the operating frequency, as follows:
9) The write recovery time of t
Figure 47
Data Sheet
Parameter
WRITE recovery time
PRECHARGE command period
Refresh period (4096 rows)
Self refresh exit time
no. of clock cycles = specified delay / clock period; round up to next integer.
With f
recovery time in all applications.
T
T
(CLK) > 1 ns, a value of (t
> 1 ns, a value of [0.5 x (t
CK
C
> 72 MHz two clock cycles for t
≤ 70 °C (comm.); -25 °C ≤ T
AC Characteristics
Test Load for DQ Pins
AC
and t
OH
parameters are measured with a 30 pF capacitive load only as shown in
WR
T
T
/2 - 0.5) ns has to be added to this parameter.
= 14 ns allows the use of one clock cycle for the write recovery time when f
- 1)] ns has to be added to this parameter.
1)2)3)4)
C
(cont’d)
WR
≤ 85 °C (ext.); V
IH
are mandatory. Qimonda recommends to use two clock cycles for the write
and V
IL
; all AC characteristics assume t
DD
47
= V
DDQ
= 1.70V to 1.95V;
Electrical CharacteristicsAC Characteristics
t
t
t
t
Symbol
WR
RP
REF
SREX
HY[B/E]18L128160B[C/F]-7.5
14
19
—
1
T
min.
= 1 ns.
128-Mbit Mobile-RAM
- 7.5
Figure
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64
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05282004-NZNK-8T0D
max.
Rev. 1.71, 2007-01
47.
ns
ns
ms
t
CK
Unit Notes
CK
≤ 72 MHz.
9)
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