HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 40

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

Table 14
1) These parameters account for the number of clock cycles and depend on the operating frequency as follows:
2.4.10
Figure 45
Power-down is entered when CKE is registered LOW (no accesses can be in progress). If power-down occurs
when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as active power-down. Entering power-down deactivates the input
and output buffers, excluding CLK and CKE. CKE LOW must be maintained during power-down.
Power-down duration is limited by the refresh requirements of the device (t
The power-down state is synchronously exited when CKE is registered HIGH (along with a NOP or DESELECT
command). One clock delay is required for power down entry and exit.
Data Sheet
Parameter
ACTIVE to ACTIVE command period
PRECHARGE command period
Refresh period (4096 rows)
Self refresh exit time
no. of clock cycles = specified delay / clock period; round up to next integer.
Timing Parameters for AUTO REFRESH and SELF REFRESH
POWER DOWN
Power Down Entry Command
Symbol
t
t
t
t
RC
RP
REF
SREX
40
67
19
–
1
min.
REF
- 7.5
Functional DescriptionCommands
HY[B/E]18L128160B[C/F]-7.5
).
–
–
64
–
max.
128-Mbit Mobile-RAM
05282004-NZNK-8T0D
Rev. 1.71, 2007-01
ns
ns
ms
t
CK
Units
1)
Notes