HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 11

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

5. Whenever a boundary of the block is reached within a given sequence, the following access wraps within the
2.2.1.2
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the
burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the
burst type and the starting column address, as shown in
2.2.1.3
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a READ command and
the availability of the first piece of output data. The latency can be programmed to 2 or 3 clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available with clock
edge n + m (for details please refer to the READ command description).
2.2.1.4
When A9 = 0, the burst length programmed via A0-A2 applies to both read and write bursts; when A9 = 1, write
accesses consist of single data elements only.
2.2.1.5
The Extended Mode Register controls additional low power features of the device. These include the Partial Array
Self Refresh (PASR, bits A0-A2)), the Temperature Compensated Self Refresh (TCSR, bits A3-A4)) and the drive
strength selection for the DQs (bits A5-A6). The Extended Mode Register is programmed via the MODE
REGISTER SET command (with BA0 = 0 and BA1 = 1) and will retain the stored information until it is programmed
again or the device loses power.
The Extended Mode Register must be loaded when all banks are idle, and the controller must wait the specified
time before initiating any subsequent operation. Violating either of these requirements result in unspecified
operation.
Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Data Sheet
Field Bits
DS
TCSR [4:3]
block.
[6:5]
Burst Type
Read Latency
Write Burst Mode
Extended Mode Register
Type Description
w
w
Selectable Drive Strength
00
01
Note: All other bit combinations are RESERVED.
Temperature Compensated Self Refresh
XX
B
B
B
Full Drive Strength
Half Drive Strength (default)
Superseded by on-chip temperature sensor (see text)
11
Table
6.
Functional DescriptionRegister Definition
HY[B/E]18L128160B[C/F]-7.5
128-Mbit Mobile-RAM
05282004-NZNK-8T0D
Rev. 1.71, 2007-01