HYB18L128160BC-7.5 QIMONDA [Qimonda AG], HYB18L128160BC-7.5 Datasheet - Page 14

• Manufacturer Part Number: HYB18L128160BC-7.5
• Description: DRAMs for Mobile Applications 128-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4
Table 7
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A11 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE
5) A10 LOW: BA0, BA1 determine which bank is precharged.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read
Address (A0 - A11, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM)
are all registered on the positive edge of CLK.
commands and operations.
Data Sheet
Command
NOP DESELECT
ACT ACTIVE (Select bank and row)
RD
WR
BST BURST TERMINATE or
PRE PRECHARGE (Deactivate row in bank or banks)
ARF AUTO REFRESH or
MRS MODE REGISTER SET
–
–
persistent), A10 LOW disables the Auto Precharge feature.
command is defined for READ or WRITE bursts with Auto Precharge disabled only.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
combinations of BA0, BA1 are reserved; A0 - A11 provide the op-code to be written to the selected mode register.
cycles;
DQM HIGH: data present on DQs are masked and thus not written to memory during write cycles; DQ output buffers are
placed in High-Z state (two clocks latency) during read cycles.
NO OPERATION
READ (Select bank and column and start read burst)
WRITE (Select bank and column and start write burst) L
DEEP POWER DOWN
SELF REFRESH (enter self refresh mode)
Data Write / Output Enable
Write Mask / Output Disable (High-Z)
Commands
Command Overview
Figure 5
14
shows the basic timing parameters, which apply to all
H
L
L
L
L
L
L
–
–
CS RAS CAS WE DQM
L
X
H
L
H
H
H
L
L
–
–
L
X
H
H
L
L
H
H
L
L
–
–
Functional DescriptionCommands
HY[B/E]18L128160B[C/F]-7.5
X
H
H
H
L
L
L
H
L
–
–
128-Mbit Mobile-RAM
X
X
X
L/H
L/H
X
X
X
X
L
H
05282004-NZNK-8T0D
X
X
Bank / Row
Bank / Col
Bank / Col
X
Code
X
Op-Code
–
–
Rev. 1.71, 2007-01
Address
Notes
1)
2)
3)
4)
5)
6)7)
8)
9)