ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 120

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
ELECTRICAL CHARACTERISTICS (cont’d)
13.10 COMMUNICATION INTERFACE CHARACTERISTICS
13.10.1 SPI - Serial Peripheral Interface
Subject to general operating conditions for V
f
Figure 96. SPI Slave Timing Diagram with CPHA = 0
Notes:
1. Data based on design simulation, not tested in production.
2. When no communication is on-going, the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3 x V
4. Depends on f
120/138
OSC
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SCK
t
r(SCK)
f(SCK)
su(SS)
h(SS)
w(SCKH)
su(MI)
su(SI)
h(MI)
a(SO)
dis(SO)
v(SO)
h(SO)
v(MO)
h(MO)
w(SCKL)
h(SI)
c(SCK)
Symbol
MISO
MOSI
, and T
1)
= 1 /
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
1)
SS
CPHA = 0
CPOL = 0
CPHA = 0
CPOL = 1
1)
1)
OUTPUT
INPUT
INPUT
A
SPI clock frequency
SPI clock rise and fall time
SS setup time
SS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
unless otherwise specified.
CPU
See note 2
. For example, if f
Parameter
t
a(SO)
t
su(SS)
t
su(SI)
4)
CPU
MSB IN
t
t
w(SCKH)
w(SCKL)
MSB OUT
= 8 MHz, then t
Master, f
Slave, f
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave (after enable edge)
Master (after enable edge)
t
t
h(SI)
c(SCK)
CPU
Conditions
CPU
t
DD
v(SO)
= 8 MHz
,
DD
CPU
= 8 MHz
BIT6 OUT
and 0.7 x V
= 1 / f
Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).
3)
CPU
BIT1 IN
= 125ns and t
DD
f
.
CPU
t
h(SO)
(4 x T
/ 128 = 0.0625
Min
CPU
120
100
100
See I/O port pin description
90
0
0
0
0
t
t
r(SCK)
f(SCK)
su(SS)
) + 50
LSB IN
= 550ns.
LSB OUT
f
f
t
h(SS)
CPU
CPU
Max
240
120
120
120
/ 4 = 2
/ 2 = 4
t
dis(SO)
MHz
Unit
See
note 2
ns