ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 30

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
7.6.3 Register Description
SYSTEM INTEGRITY (SI) CONTROL/STATUS
REGISTER (SICSR)
Read/Write
Reset Value: 0110 0xx0 (6xh)
Bit 7 = Reserved (should be 0)
Bits 6:5 = CR[1:0] RC Oscillator Frequency Ad-
justment bits
These bits, as well as CR[9:2] bits in the RCCR
register must be written immediately after reset to
adjust the RC oscillator frequency and to obtain an
accuracy of 1%. Refer to
Bit 4 = WDGRF Watchdog Reset flag
This bit indicates that the last Reset was generat-
ed by the Watchdog peripheral. It is set by hard-
ware (watchdog reset) and cleared by software
(writing zero) or an LVD Reset (to ensure a stable
cleared state of the WDGRF flag when CPU
starts).
Combined with the LVDRF flag information, the
flag description is given in the following table.
Bit 3 = LOCKED PLL Locked Flag
This bit is set and cleared by hardware. It is set au-
tomatically when the PLL reaches its operating fre-
quency.
0: PLL not locked
1: PLL locked
30/138
1
External RESET pin
Watchdog
LVD
Res
7
CR1
RESET Sources
CR0
WDG
RF
LOCKED
section 7.3 on page
LVDRF
LVD
RF
0
0
1
Res
WDGRF
X
0
1
Res
22.
0
Bit 2 = LVDRF LVD reset flag
This bit indicates that the last Reset was generat-
ed by the LVD block. It is set by hardware (LVD re-
set) and cleared by software (by reading). When
the LVD is disabled by OPTION BYTE, the LVDRF
bit value is undefined.
Bits 1:0 = Reserved (should be 0)
Application notes
The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.
PLL TEST REGISTER (PLLTST)
Read/Write
Reset Value: 0000 0000(00h)
Bit 7: PLLdiv2 PLL clock divide by 2
This bit is read or write by software and cleared by
hardware after reset. This bit divides the PLL out-
put clock by 2.
0: PLL output clock
1: Divide by 2 of PLL output clock
Refer to
page
Note: Write of this bit is effective after two t
cles (if system clock is 8 MHz) or else one cycle (if
system clock is 4 MHz), that is, effective time is
250ns.
Bits 6:0: Reserved, must always be cleared.
PLLdiv2
7
23.
“Clock Management Block Diagram” on
0
0
0
0
0
0
CPU
0
0
cy-