ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 56

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)
11.2.3.2 Dead Time Generation
A dead time can be inserted between PWM0 and
PWM1 using the DTGR register. This is required
for half-bridge driving where PWM signals must
not be overlapped. The non-overlapping PWM0/
PWM1 signals are generated through a program-
mable dead time by setting the DTE bit.
Dead time value = DT[6:0] x Tcounter1
DTGR[7:0] is buffered inside so as to avoid de-
forming the current PWM cycle. The DTGR effect
will take place only after an overflow.
Figure 37. Dead Time Generation
In the above example, when the DTE bit is set:
– PWM goes low at DCR0 match and goes high at
– PWM1 goes high at DCR0 + T
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1
ATR1 + T
ATR match.
CK_CNTR1
CNTR1
PWM 0
PWM 1
PWM 0
PWM 1
dt
counter = DCR0
DCR0
dt
DCR0+1
T
and goes low at
counter1
T
dt
counter = DCR1
OVF
Notes:
1. Dead time is generated only when DTE = 1 and
DT[6:0] ≠ 0. If DTE is set and DT[6:0] = 0, PWM
output signals will be at their reset state.
2. Half-bridge driving is possible only if polarities of
PWM0 and PWM1 are not inverted, that is, if OP0
and OP1 are not set. If polarity is inverted, overlap-
ping PWM0/PWM1 signals will be generated.
3. Dead Time generation does not work at 1ms
timebase.
With this programmable delay (T
and PWM1 signals which are generated are not
overlapped.
T
dt
= DT[6:0] x T
ATR1
counter1
T
dt
dt
), the PWM0