ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 25

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SUPPLY, RESET AND CLOCK MANAGEMENT (cont’d)
7.5 RESET SEQUENCE MANAGER (RSM)
7.5.1 Introduction
The reset sequence manager includes three RE-
SET sources as shown in
■
■
■
Note: A reset can also be triggered following the
detection of an illegal opcode or prebyte code. Re-
fer to
These sources act on the RESET pin which is al-
ways kept low during the delay phase.
The RESET service routine vector is fixed at ad-
dresses FFFEh-FFFFh in the ST7 memory map.
The basic RESET sequence consists of three
phases as shown in
■
■
■
Caution: When the ST7 is unprogrammed or fully
erased, the Flash is blank and the RESET vector
is not programmed. For this reason, it is recom-
mended to keep the RESET pin in low state until
programming mode is entered, in order to avoid
unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the
oscillator to stabilize and ensures that recovery
has taken place from the RESET state. The short-
er or longer clock cycle delay is automatically se-
lected depending on the clock source chosen by
option byte:
Internal RC Oscillator
External clock (connected to CLKIN pin)
External Crystal/Ceramic Oscillator
(connected to OSC1/OSC2 pins)
External RESET source pulse
Internal LVD RESET (Low Voltage Detection)
Internal WATCHDOG RESET
Active Phase depending on the RESET source
256 or 4096 CPU clock cycle delay (see table
below)
RESET vector fetch
section 12.2.1 on page 95
Clock Source
Figure
Figure
13:
for further details.
14:
Cycle Delay
CPU Clock
4096
256
256
The RESET vector fetch phase duration is two
clock cycles.
If the PLL is enabled by option byte, it outputs the
clock after an additional delay of t
Figure 11 on page
Figure 13. RESET Sequence Phases
7.5.2 Asynchronous External RESET Pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
Section 13 ELECTRICAL CHARACTERISTICS
for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized (see
tection is asynchronous and therefore the MCU
can enter the RESET state even in HALT mode.
Active Phase
256 or 4096 CLOCK CYCLES
INTERNAL RESET
22).
RESET
ON
weak pull-up resistor.
Figure
ST7L15, ST7L19
STARTUP
15). This de-
VECTOR
h(RSTL)in
FETCH
25/138
(see
in
1