ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 67

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)
BREAK CONTROL REGISTER (BREAKCR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = Reserved, must be kept cleared
Bit 6 = BREDGE Break Input Edge Selection (not
applicable to ROM devices)
This bit is read/write by software and cleared by
hardware after reset. It selects the active level of
Break signal.
0: Low level of Break selected as active level.
1: High level of Break selected as active level.
Bit 5 = BA Break Active
This bit is read/write by software, cleared by hard-
ware after reset and set by hardware when the
BREAK pin is low. It activates/deactivates the
Break function.
0: Break not active
1: Break active
Bit 4 = BPEN Break Pin Enable
This bit is read/write by software and cleared by
hardware after Reset.
0: Break pin disabled
1: Break pin enabled
Bits 3:0 = PWM[3:0] Break Pattern
These bits are read/write by software and cleared
by hardware after a reset. They are used to force
the four PWMx output signals into a stable state
when the Break function is active and correspond-
ing OEx bit is set.
PWMx DUTY CYCLE REGISTER HIGH (DCRxH)
Read / Write
Reset Value: 0000 0000 (00h)
7
0
BREDGE
BA
BPEN
PWM3 PWM2 PWM1 PWM0
0
PWMx DUTY CYCLE REGISTER LOW (DCRxL)
Read / Write
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared
Bits 11:0 = DCRx[11:0] PWMx Duty Cycle Value
This 12-bit value is written by software. It defines
the duty cycle of the corresponding PWM output
signal (see
In PWM mode (OEx = 1 in the PWMCR register)
the DCR[11:0] bits define the duty cycle of the
PWMx output signal (see
Compare mode, they define the value to be com-
pared with the 12-bit upcounter value.
INPUT CAPTURE REGISTER HIGH (ATICRH)
Read only
Reset Value: 0000 0000 (00h)
INPUT CAPTURE REGISTER LOW (ATICRL)
Read only
Reset Value: 0000 0000 (00h)
Bits 15:12 = Reserved, must be kept cleared
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
ICR7
15
15
0
7
0
7
ICR6
0
0
Figure
ICR5
0
0
35).
ICR4
0
0
DCR11 DCR10 DCR9 DCR8
ICR11 ICR10
ICR3
Figure
ST7L15, ST7L19
ICR2
35). In Output
ICR9
ICR1
67/138
ICR8
ICR0
8
8
0
0
1