ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 37

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

POWER SAVING MODES (cont’d)
9.4 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when ACTIVE HALT is disabled
(see
when the AWUEN bit in the AWUCSR register is
cleared.
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Mapping,” on page
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start-up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
ure
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes up im-
mediately.
In HALT mode, the main oscillator is turned off,
stopping all internal processing, including the op-
eration of the on-chip peripherals. All peripherals
are not clocked except those which receive their
clock supply from another clock generator (such
as an external or auxiliary oscillator).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction,
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
tion 15.1 on page 126
Figure 22. HALT Timing Overview
[Active Halt disabled]
INSTRUCTION
RUN
23).
section 9.5 on page 38
HALT
HALT
256 OR 4096 CPU
32) or a RESET. When exiting
CYCLE DELAY
INTERRUPT
for more details).
RESET
OR
for more details) and
Table 5, “Interrupt
VECTOR
FETCH
RUN
sec-
Fig-
Figure 23. HALT Mode Flowchart
Notes:
1. WDGHALT is an option bit. See option byte section for
more details.
2. Peripheral clocked with an external clock source can
still be active.
3. Only some specific interrupts can exit the MCU from
HALT mode (such as external interrupt). Refer to
“Interrupt Mapping,” on page 32
4. Before servicing an interrupt, the CC register is pushed
on the stack. The I bit of the CC register is set during the
interrupt routine and cleared when the CC register is
popped.
5. If the PLL is enabled by option byte, it outputs the clock
after a delay of t
(AWUCSR.AWUEN=0)
HALT INSTRUCTION
(Active Halt disabled)
N
WATCHDOG
WDGHALT
RESET
1
INTERRUPT
Y
STARTUP
1)
3)
ENABLE
(see
256 OR 4096 CPU CLOCK
OR SERVICE INTERRUPT
0
FETCH RESET VECTOR
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
OSCILLATOR
PERIPHERALS
CPU
I BIT
CPU
I BIT
CPU
I BIT
N
Figure 11 on page
CYCLE
for more details.
ST7L15, ST7L19
RESET
Y
WATCHDOG
DELAY
DISABLE
2)
OFF
OFF
OFF
OFF
ON
ON
5)
ON
ON
ON
X
X
0
Table 5,
22).
4)
4)
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