ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 51

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ON-CHIP PERIPHERALS (cont’d)
The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. This downcounter is free-
running: It counts down, even if the watchdog is
disabled. The value to be stored in the CR register
must be between FFh and C0h (see
.Watchdog
– The WDGA bit is set (watchdog enabled).
– The T6 bit is set to prevent generating an imme-
– The T[5:0] bits contain the number of increments
Following a reset, the watchdog is disabled. Once
activated, it can be disabled only by a reset.
The T6 bit can generate a software reset (the
WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
generates a Reset.
Table 12.Watchdog Timing
Notes:
1. The timing variation shown in
the unknown status of the prescaler when writing
to the CR register.
2. The number of CPU clock cycles applied during
the RESET phase (256 or 4096) must be taken
into account in addition to these timings.
11.1.4 Hardware Watchdog Option
If Hardware Watchdog is selected by the option
byte, the watchdog is always active and the
WDGA bit in the CR is not used.
Refer to the Option Byte description in
on page
Table 13. Watchdog Timer Register Map and Reset Values
diate reset.
which represents the time delay before the
watchdog produces a reset.
Address
Counter Code
002Eh
(Hex.)
WDG
C0h
FFh
126.
Timing):
WDGCR
Reset Value
Register
Label
f
CPU
= 8 MHz
(ms)
min
127
1
WDGA
7
0
Table 12
T6
6
1
section 15
(ms)
max
128
Table 12
2
is due to
T5
5
1
11.1.4.1 Using Halt Mode with the WDG
(WDGHALT Option)
If HALT mode with Watchdog is enabled by the op-
tion byte (no watchdog reset on HALT instruction),
it is recommended before executing the HALT in-
struction to refresh the WDG counter, to avoid an
unexpected WDG reset immediately after waking
up the microcontroller (same behavior in ACTIVE
HALT mode).
11.1.5 Interrupts
None.
11.1.6 Register Description
CONTROL REGISTER (WDGCR)
Read/Write
Reset Value: 0111 1111 (7Fh)
Bit 7 = WDGA Activation bit.
This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled
Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.
Bits 6:0 = T[6:0] 7-bit timer (MSB to LSB).
These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).
WDGA
7
T4
4
1
T6
T3
3
1
T5
T4
T2
2
1
T3
ST7L15, ST7L19
T2
T1
1
1
T1
51/138
T0
0
1
T0
0
1