ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 90

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
10-BIT A/D CONVERTER (ADC) (cont’d)
11.5.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write (Except bit 7 read only)
Reset Value: 0000 0000 (00h)
Bit 7 = EOC End of Conversion
This bit is set by hardware. It is cleared by soft-
ware reading the ADCDRH register.
0: Conversion is not complete
1: Conversion complete
Bit 6 = SPEED ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription (ADCDRL register).
Bit 5 = ADON A/D Converter on
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bits 4:3 = Reserved (must be kept cleared)
Bits 2:0 = CH[2:0] Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*The number of channels is device dependent.
Refer to the device pinout description.
90/138
1
EOC SPEED ADON
7
Channel Pin*
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
0
0
CH2
0
0
0
0
1
1
1
CH2
CH1
CH1
0
0
1
1
0
0
1
CH0
CH0
0
1
0
1
0
1
0
0
DATA REGISTER HIGH (ADCDRH)
Read Only
Reset Value: xxxx xxxx (xxh)
Bits 7:0 = D[9:2] MSB of Analog Converted Value
AMP CONTROL/DATA REGISTER LOW (AD-
CDRL)
Read/Write
Reset Value: 0000 00xx (0xh)
Bits 7:5 = Reserved (forced by hardware to 0)
Bit 4 = Reserved (must be kept cleared)
Bit 3 = SLOW Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit in the ADCCSR regis-
ter to configure the ADC clock speed as shown on
the table below.
Note: Max f
13.11 on page
Bit 2 = Reserved (must be kept cleared)
Bits 1:0 = D[1:0] LSB of Analog Converted Value
D9
7
7
0
D8
0
ADC
D7
f
f
122)
0
f
CPU
CPU
f
ADC
CPU
allowed = 4 MHz (see
/2
/4
D6
-
SLOW
D5
D4
-
SLOW SPEED
0
0
1
D3
D1
section
0
1
x
D2
D0
0
0