ST7FL15F1MAE STMICROELECTRONICS [STMicroelectronics], ST7FL15F1MAE Datasheet - Page 64

• Manufacturer Part Number: ST7FL15F1MAE
• Description: 8-bit MCU for automotive with single voltage Flash/ROM memory, data EEPROM, ADC, 5 timers, SPI
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7L15, ST7L19
DUAL 12-BIT AUTORELOAD TIMER 4 (cont’d)
11.2.3.7 Force Update (available only on Flash
devices)
In order not to wait for the counter
load the value into active DCRx registers, a pro-
grammable counter
both counters, a separate bit is provided which
when set, starts the counters with the overflow val-
ue, that is FFFh. After overflow, the counters start
counting from their respective autoreload register
values.
Figure 47. Force Overflow Timing Diagram
11.2.4 Low Power Modes
11.2.5 Interrupts
Note: The CMP and AT4 IC events are connected
to the same interrupt vector. The OVF event is
mapped on a separate vector (see Interrupts chap-
64/138
1
Mode
WAIT
HALT
Interrupt
Overflow
Event
AT4 IC
Event
CMP
Event
Overflow
Event2
Event
FORCE2
Description
No effect on AT timer
AT timer halted
OVF1
ICF
CMPFx
OVF2
Event
Flag
FORCEx
CNTRx
f
CNTRx
Control
OVFIE1
ICIE
CMPIE
OVFIE2
FORCE1
Enable
x
Bit
overflow is provided. For
ATCSR2 Register
from
Wait
Exit
Yes
E03
from
Exit
Halt
x
No
E04
overflow to
Active
from
Halt
Exit
Yes
No
FFF
These bits are FORCE1 and FORCE2 in the
ATCSR2 register. FORCE1 is used to force an
overflow on Counter 1 and FORCE2 is used for
Counter 2. These bits are set by software and re-
set by hardware after the respective counter over-
flow event has occurred.
This feature can be used at any time. All related
features such as PWM generation, Output Com-
pare, Input Capture and One Pulse can be used
this way.
ter). They generate an interrupt if the enable bit is
set in the ATCSR register and the interrupt mask
in the CC register is reset (RIM instruction).
ARRx