MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 105
MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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2.4.2.5
The PWM module is connected to port P. Port P pins can be used as PWM outputs. Further the Keypad
Wake-Up function is implemented on pins PP[7:0]. During reset, port P pins are configured as high-
impedance inputs.
Port P offers 8 general purpose I/O pins with edge triggered interrupt capability in wired-or fashion. The
interrupt enable as well as the sensitivity to rising or falling edges can be individually configured on per
pin basis. All 8 bits/pins share the same interrupt vector. Interrupts can be used with the pins configured
as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in STOP
or WAIT mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
Freescale Semiconductor
2-38).
Port P
1. These values include the spread of the oscillator frequency over temperature,
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
voltage and process.
Uncertain
Ignored
Pulse
Figure 2-47. Interrupt Glitch Filter on Port P and J (PPS = 0)
Valid
Table 2-38. Pulse Detection Criteria
3 < t
t
t
pign
Figure 2-48. Pulse Illustration
pval
t
Value
pign
pulse
<= 3
>= 4
STOP Mode
(Figure
t
pval
< 4
MC9S12Q128
Rev 1.09
t
pulse
2-48) shorter than a specified time from generating an
Bus clocks
Bus clocks
Bus clocks
Unit
Chapter 2 Port Integration Module (PIM9C32) Block Description
3.2 < t
t
pign
t
pval
STOP
Value
pulse
<= 3.2
>= 10
(1)
< 10
Mode
Unit
s
s
s
(Figure 2-47
and
105
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