MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 106

• Manufacturer Part Number: MC9S12Q
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 2 Port Integration Module (PIM9C32) Block Description
A valid edge on input is detected if 4 consecutive samples of a passive level are followed by 4 consecutive
samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by a single RC oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
2.4.2.6
In all modes, port J pins PJ[7:6] can be used for general purpose I/O or interrupt driven general purpose
I/O’s. During reset, port J pins are configured as inputs.
Port J offers 2 I/O ports with the same interrupt features as on port P.
2.4.3
All port and pin logic is located in the core module. Please refer to S12_mebi Block User Guide for details.
2.4.4
All ports start up as general purpose inputs on reset.
2.4.5
2.4.5.1
No low power options exist for this module in run mode.
2.4.5.2
No low power options exist for this module in wait mode.
2.4.5.3
All clocks are stopped. There are asynchronous paths to generate interrupts from STOP on port P and J.
2.5
The reset values of all registers are given in
2.5.1
All registers including the data registers get set/reset asynchronously.
properties after reset initialization.
106
Initialization Information
Port A, B, E and BKGD Pin
External Pin Descriptions
Low Power Options
Reset Initialization
Port J
Run Mode
Wait Mode
Stop Mode
Section 2.3.2, “Register
MC9S12Q128
Rev 1.09
Descriptions”.
Table 2-39
summarizes the port
Freescale Semiconductor