MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 252

• Manufacturer Part Number: MC9S12Q
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
9.1.2
This subsection lists and briefly describes all operating modes supported by the CRG.
9.1.3
Figure 9-1
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Run mode
All functional parts of the CRG are running during normal run mode. If RTI or COP functionality
is required the individual bits of the associated rate select registers (COPCTL, RTICTL) have to be
set to a nonzero value.
Wait mode
This mode allows to disable the system and core clocks depending on the configuration of the
individual bits in the CLKSEL register.
Stop mode
Depending on the setting of the PSTP bit, stop mode can be differentiated between full stop mode
(PSTP = 0) and pseudo-stop mode (PSTP = 1).
— Full stop mode
— Pseudo-stop mode
Self-clock mode
Self-clock mode will be entered if the clock monitor enable bit (CME) and the self-clock mode
enable bit (SCME) are both asserted and the clock monitor in the oscillator block detects a loss of
clock. As soon as self-clock mode is entered the CRGV4 starts to perform a clock quality check.
Self-clock mode remains active until the clock quality check indicates that the required quality of
the incoming clock signal is met (frequency and amplitude). Self-clock mode should be used for
safety purposes only. It provides reduced functionality to the MCU in case a loss of clock is causing
severe system conditions.
shows a block diagram of the CRGV4.
The oscillator is disabled and thus all system and core clocks are stopped. The COP and the
RTI remain frozen.
The oscillator continues to run and most of the system and core clocks are stopped. If the
respective enable bits are set the COP and RTI will continue to run, else they remain frozen.
Modes of Operation
Block Diagram
MC9S12Q128
Rev 1.09
Freescale Semiconductor