MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 356
MC9S12Q
Manufacturer Part Number
MC9S12Q
Description
Microcontrollers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
1.MC9S12Q.pdf
(644 pages)
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Chapter 12 Pulse-Width Modulator (PWM8B4C) Block Description
12.3.2.5
The PWMCAE register contains control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 12.4.2.5, “Left Aligned Outputs,”
detailed description of the PWM output modes.
Read: anytime
Write: anytime
356
Module Base + 0x0004
Reset
CAE3
CAE2
Field
3
2
W
R
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
PWM Center Align Enable Register (PWMCAE)
0
0
7
Write these bits only when the corresponding channel is disabled.
= Unimplemented or Reserved
PCKA2
Figure 12-7. PWM Center Align Enable Register (PWMCAE)
0
0
0
0
1
1
1
1
0
0
6
Table 12-7. PWMCAE Field Descriptions
Table 12-6. Clock A Prescaler Selects
PCKA1
0
5
0
0
1
1
0
0
1
1
and
Section 12.4.2.6, “Center Aligned Outputs,”
MC9S12Q128
Rev 1.09
NOTE
0
4
PCKA0
0
1
0
1
0
1
0
1
Description
CAE3
0
3
Value of Clock A
Bus Clock / 128
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock
CAE2
0
2
Freescale Semiconductor
CAE1
0
1
for a more
CAE0
0
0
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