MC9S12Q FREESCALE [Freescale Semiconductor, Inc], MC9S12Q Datasheet - Page 270

• Manufacturer Part Number: MC9S12Q
• Description: Microcontrollers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Chapter 9 Clocks and Reset Generator (CRGV4) Block Description
of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and
CPU activity ceases.
9.4.3
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The CRGV4 then asserts self-clock mode or generates a system reset
depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected
no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME
control bit.
9.4.4
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
A time window of 50000 VCO clock cycles
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See
1. VCO clock cycles are generated by the PLL when running at minimum frequency f
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BUS CLOCK / ECLK
CORE CLOCK:
Power-on reset (POR)
Low voltage reset (LVR)
Wake-up from full stop mode (exit full stop)
Clock monitor fail indication (CM fail)
Clock Monitor (CM)
Clock Quality Checker
OSCCLK
VCO
clock
Figure 9-18. Core Clock and Bus Clock Relationship
1
1 2 3 4 5
Figure 9-19. Check Window Example
check window
2
1
3
is called check window.
MC9S12Q128
Rev 1.09
4095
osc ok
4096
Figure 9-19
SCM
49999
.
as an example.
50000
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