TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 26

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
Programming
The instruction set for the C251 Architecture is a superset of the instruction set for the C51 Architecture. This chapter
describes the addressing modes and summarizes the instruction set, which is divided into data instructions, bit
instructions, and control instructions. (Chapter 5, “Instruction Set Reference” contains an opcode map and the detailed
description of each instruction.)
Notes:
4.1. Source Mode or Binary Mode Opcodes
Source mode and Binary mode refer to the two ways of assigning opcodes to the instruction set of the C251
Architecture. Depending on the application, one mode or the other may produce more efficient code. The mode is
established during device reset based on the value of the SRC bit in configuration byte CONFIG0. For information
regarding the configuration bytes, see the Product Design Guide.
Binary mode and source mode refer to two ways of assigning opcodes to the instruction set for the C251 Architecture.
One of these modes must be selected when the chip is configured. Depending on the application, binary mode or source
mode may produce more efficient code. This section describes the binary and source modes and provides some
guidelines for selecting the mode for your application.
The C251 Architecture has two types of instructions:
Figure 4.1. shows the opcode map for the binary mode. Area I and area II make up the opcode map for the instructions
that are unique to the C251 Architecture. Note that some of these opcodes are reserved for future instructions. The
opcode values for areas II and III are identical (06H–FFH). To distinguish between the two areas in binary mode, the
opcodes in area III are given the prefix A5H (the A5H instruction is not implemented in the native C51 Architecture).
The area III opcodes are thus A506H–A5FFH.
In source mode, opcodes for instructions in area II require the A5F escape prefix while opcodes for instructions in area
III (C251 Architecture) do not.
To illustrate the difference between the binary–mode and source–mode opcodes, Table 4.1. shows the opcode
assignments for three sample instructions.
Figure 4.2. shows the opcode map for source mode. Areas II and III have switched places (compare with Figure 4.1. ).
The instruction execution times given in Chapter 5 are for code executing from on–chip code memory and for data
that is read from and written to on–chip RAM. Execution times are increased by executing code from external
memory, accessing peripheral SFRs, accessing data in external memory, using a wait state, or extending the ALE
pulse.
For some instructions, accessing the port SFRs, Px (x = 0, 1, 2, 3) increases the execution time. These cases are
noted individually in the tables in Chapter 5.
Instructions that originate in the C51 Architecture
Instructions that are unique to the C251 Architecture
DEC A
SUBB A, R4
SUB R4, R4
Table 4.1. Examples of Opcodes in Binary and Source Modes
Instruction
14H
9CH
A59CH
Binary Mode
Opcode
14CH
A59CH
9CH
Source Mode
TSC80251
4.1