TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 61

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
Notes:
1.
2.
3.
4.
5.16
Absolute jump
Extended jump
opnd
Long jump
opnd
Short jump
Jump indirect
(DPTR)
No operation
AJMP
EJMP
EJMP
LJMP
LJMP
SJMP
JMP
NOP
Mnemonic
Mnemonic
A shaded cell denotes an instruction in the C51 Architecture.
In internal execution only, add 1 to the number of states if the destination address is internal and odd.
Add 2 to the number of states if the destination address is external.
Add 3 to the number of states if the destination address is external.
addr11
addr24
@DRk
@WRj
addr16
rel
@A +DPTR
<src>
<dest>,
<dest>,
(1)
Table 5.20. Summary of unconditional Jump Instructions
AJMP <src>
EJMP <src>
LJMP <src>
SJMP rel
JMP @A +DPTR
NOP
Absolute jump
Extended jump
Extended jump (indirect)
Long jump (indirect)
Long jump (direct address)
Short jump (relative address)
Jump indirect relative to the DPTR
No operation (Jump never)
Comments
Comments
(PC)
(PC)
(PC)
(PC)
(PC)
(PC)
23:16
(PC) + size (instr); (PC)
(PC) + size (instr); (PC)
(PC) +2; (PC)
(PC) +1
(PC) +2; (PC)
Bytes
Binary Mode
2
5
3
3
3
2
1
1
FFh; (PC)
States
3
6
7
6
5
4
5
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
1
10:0
15:0
Rev. C – May 7, 1999
(PC) +rel
Bytes
Source Mode
src opnd
(A) +
2
4
2
2
3
2
1
1
23:0
15:0
States
3
5
6
5
5
4
5
(2)(3)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
(2)(4)
src
src
1