TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 40

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.6.7. Variable Interrupt Parameters
Both response time and latency calculations contain fixed and variable components. By definition, it is often difficult
to predict exact timing calculations for real-time requests. One large variable is the completion time of an instruction
cycle coincident with the occurrence of an interrupt request. Worst-case predictions typically use the longest-executing
instruction in an Architecture’s code set. In the case of the TSC80251, the longest-executing instruction is a 16-bit
divide (DIV). However, even this 21-state instruction may have only 1 or 2 remaining states to complete before the
interrupt system injects a context switch. This uncertainty affects both response time and latency.
4.6.7.1. Response Time Variables
Response time is defined as the start of a dynamic time period when a source requests an interrupt and lasts until a break
in the current instruction execution stream occurs (See Figure 4.4. ). Response time (and therefore latency) is affected
by two primary factors : the incidence of the request relative to the four-state-time sample window and the completion
time of instructions in the response period (i.e., shorter instructions complete earlier than longer instructions).
Note:
External interrupt signals require one additional state time in comparison to internal interrupts. This is necessary to sample and latch the pin
value prior to a poll of interrupts. The sample occurs in the first half of the state time and the poll/request occurs in the second half of the next
state time. Therefore, this sample and poll/request portion of the minimum fixed response and latency time is five states for internal interrupts and
six states for external interrupts. External interrupts must remain active for at least five state times to guarantee interrupt recognition when the
request occurs immediately after a sample has been taken (i.e., requested in the second half of a sample state time).
If the external interrupt goes active one state after the sample state, the pin is not resampled for another three states.
After the second sample is taken and the interrupt request is recognized, the interrupt controller requests the context
switch. The programmer must also consider the time to complete the instruction at the moment the context switch
request is sent to the execution unit. If 9 states of a 10-state instruction have completed when the context switch is
requested, the total response time is 6 states, with a context switch immediately after the final state of the 10-state
instruction (See Figure 4.5. ).
Response Time = 6
OSC
State
Time
INT0#
Sample INT0#
Request
10–State
PUSH PC
Instruction
Figure 4.5. Response Time Example
Conversely, if the external interrupt requests service in the state just prior to the next sample, response is much quicker.
One state asserts the request, one state samples, and one state requests the context switch. If at that point the same
instruction conditions exist, one additional state time is needed to complete the 10-state instruction prior to the context
switch (See Figure 4.6. ). The total response time in this case is four state times. The programmer must evaluate all
pertinent conditions for accurate predictability.
Rev. C – May 7, 1999
4.15