TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 30

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
The PSW register is identical to the PSW register in 80C51 microcontrollers. The PSW1 register exists only in
TSC80251 microcontrollers. Bits CY, AC, RS0, RS1, and OV in PSW1 are identical to the corresponding bits in PSW,
i.e., the same bit can be accessed in either register. Table 4.4. lists the instructions that affect the CY, AC, OV, N and
Z bits.
4.4. Data Instructions
Data instructions consist of arithmetic, logical, and data–transfer instructions for 8–bit, 16–bit and 32–bit data. This
section describes the data addressing modes and the set of data instructions.
4.4.1. Data Addressing Modes
This section describes the data addressing modes, which are summarized in two tables: Table 4.6. for the instructions
that are native to the C51 Architecture and Table 4.6. for the data instructions unique to the C251 Architecture.
Notes:
4.4.1.1. Addressable Registers
Both Architectures address registers directly.
Notes :
1. X = the flag can be affected by the instruction. 0 = the flag is cleared by the instruction.
2. The AC flag is affected only by operations on 8–bit operands.
3. If the divisor is zero, the OV flag is set, and the other bits are meaningless.
4. For SRL, SLL and SRA instructions, the last bit shifted out is stored in the CY bit.
Instruction
Instruct on
References to registers R0-R7, WR0-WR6, DR0 and DR4 always refer to the register bank that is currently selected
by the PSW and PSW1 registers. Registers in all banks (active and inactive) can be accessed as memory locations
in the range 00h-1Fh.
Instructions from the C51 Architecture access external memory through the region of memory specified by byte
DPXL in the extended data pointer register, DPX (DR56). Following reset, DPXL contains 01h, which maps the
external memory to region 01:. You can specify a different region by writing to DR56 or the DPXL SFR.
C251 Architecture
In the register addressing mode, the operand(s) in a data instruction are in byte registers (R0-R15), word registers
(WR0, WR2, ..., WR30) or dword registers (DR0, DR4, ..., DR28, DR56, DR60).
C51 Architecture
Instructions address registers R0-R7 only.
Arithmetic
Program
Logical
C
Control
Type
g
l
Table 4.4. The Efffects of Instructions on the PSW and PSW1 Flags
ADD, ADDC, SUB, CMP
INC, DEC
MUL, DIV
DA
ANL, ORL, XRL, CLR A, CPL A, RL, RR, SWAP
RLC, RRC, SRL, SLL, SRA
CJNE
DJNE
(3)
Instruction
Instruction
(4)
CY
X
X
X
X
0
OV
X
X
Flags Affected
TSC80251
AC
X
(2)
(1)
N
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Z
4.5