TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 32

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

Rev. C – May 7, 1999
Register
Immediate 2 bits
Immediate 8 bits
Immediate 16 bits
Di
Direct, 8 address bits
Direct, 16 address bits
Indirect, 16 address
bits
Indirect, 24 address
bits
Displacement, 16
address bits
Displacement, 24
address bits
Notes:
1. These registers are accessible in the memory space as well as in the register file.
2. The C251 Architecture supports SFRs in locations S:000h-S:1FFh.
C51 Architecture
Instructions use indirect addressing to access on–chip RAM, code memory, and external data RAM.
Dword register (@DRk, k = 0, 4, 8, ..., 28, 56, and 60)
The 24 least significant bits can access the entire 16–Mbyte address space. The upper eight bits of DRk must
be 0. (If you use DR60 as a general data pointer, be aware that DR60 is the extended stack pointer register SPX.)
Byte register (@Ri, i = 0, 1)
Registers R0 and R1 indirectly address on–chip memory locations 00h-FFh and the lowest 256 bytes of external
data RAM.
16–bit data pointer (@DPTR or @A+DPTR)
The MOVC and MOVX instructions use these indirect modes to access code memory and external data RAM.
16–bit program counter (@A+PC)
The MOVC instruction uses this indirect mode to access code memory.
8 dd
Mode
Table 4.6. Addressing Modes for Data Instruction in the C251 Architecture
bi
00:0000h-00:001Fh
N.A. (Operand is in
the instruction)
N.A. (Operand is in
the instruction)
N.A. (Operand is in
the instruction)
00:0000h-00:007Fh
SFRs
00:0000h-00:FFFFh
00:0000h-00:FFFFh
00:0000h-FF:FFFFh
00:0000h-00:FFFFh
00:0000h-FF:FFFFh
Address Range of
Operand
R0-R15, WR0-WR30,
DR0-DR28, DR56, DR60
#short = 1, 2, or 4
#data8 = #00h-#FFh
#data16 = #0000h-#FFFFh
dir8 = 00:0000h-00:007Fh
dir8 = S:080h-S:1FFh (2)
or SFR mnemonic
dir16 = 00:0000h-00:FFFFh
@WR0-@WR30
@DR0-@DR30, @DR56,
@DR60
@WRj +dis16 =
@WR0 +0h through
@WR30 +FFFFh
@DRk +dis24 =
@DR0 +0h through @DR28
+FFFFh,
@DR56 +(0h-FFFFh),
@DR60 +(0h-FFFFh)
Assembly Language
Reference
R0-R7, WR0-WR6, and DR4 are
in the register bank currently
selected by the PSW and PSW1
Used only in increment and
decrement instructions
On-chip RAM
SFR address
Upper 8 bits of DRk must be 00h
Offset is signed; address wraps
around in region 00:
Offset is signed, upper 8 bits of
DRk must 00h
TSC80251
Comments
4.7