TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 43

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.6.10. Interrupt Vector Cycle
When an interrupt vector cycle is initiated, the CPU breaks the instruction stream sequence, resolves all instruction
pipeline decisions, and pushes multiple program counter (PC) bytes onto the stack. The CPU then reloads the PC with
a start address for the appropriate ISR. The number of bytes pushed to the stack depends upon the INTR bit in the
CONFIG1 configuration register (See Product Design Guide). The complete sample, poll, request and context switch
vector sequence is illustrated in the interrupt latency timing diagram.
Note:
If the interrupt flag for a level-triggered external interrupt is set but denied for one of the above conditions and is clear when the blocking
condition is removed, then the denied interrupt is ignored. In other words, blocked interrupt requests are not buffered for retention.
4.6.11. ISRs in Process
ISR execution proceeds until the RETI instruction is encountered. The RETI instruction informs the processor the
interrupt routine is completed. The RETI instruction in the ISR pops PC address bytes off the stack (as well as PSW1
for INTR = 1), and execution resumes at the suspended instruction stream.
Note:
A simple RET instruction also returns execution to the interrupted program. In previous implementations this inappropriately allowed the system
to operate as though an interrupt service routine is still in progress. The TSC80C251 allow use of both RETI and RET instructions for interrupt
completion. However, for code expected to run properly on both 80C51 and TSC80C251 microcontrollers, only the execution of a RETI
instruction is considered proper completion of the interrupt operation.
With the exception of TRAP, the start addresses of consecutive interrupt service routines are eight bytes apart. If
consecutive interrupts are used (IE0 and TF0, for example, or TF0 and IE1), the first interrupt routine (if more than
seven bytes long) must execute a jump to some other memory location. This prevents overlap of the start address of
the following interrupt routine.
Rev. C – May 7, 1999
4.18