TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 33

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.4.1.5. Displacement Addressing
Several move instructions use displacement addressing to move bytes or words from a source to a destination.
Sixteen–bit displacement addressing (@WRj+dis16) accesses indirectly the lowest 64 Kbytes in memory. The base
address can be in any word register WRj. The instruction contains a 16–bit signed offset which is added to the base
address. Only the lowest 16 bits of the sum are used to compute the operand address. If the sum of the base address
and a positive offset exceeds FFFFh, the computed address wraps around within region 00: (e.g. F000h + 2005h
becomes 1005h). Similarly, if the sum of the base address and a negative offset is less than zero, the computed address
wraps around the top of region 00: (e.g., 2005h + F000h becomes 1005h).
24–bit displacement addressing (@DRk+dis24) accesses indirectly the entire 16–Mbyte address space. The base
address must be in DR0, DR4, ..., DR24, DR28, DR56, or DR60. The upper byte in the dword register must be zero.
The instruction contains a 16–bit signed offset which is added to the base address.
4.4.2. Arithmetic Instructions
The set of arithmetic instructions is greatly expanded in the C251 Architecture. The ADD and SUB instructions (See
Table 5.19) operate on byte and word data that is accessed in several ways :
The ADDC and SUBB instructions are the same as those for 80C51 microcontrollers.
The CMP (compare) instruction (See Table 5.20) calculates the difference of two bytes or words and then writes to flags
CY, OV, AC, N, and Z in the PSW and PSW1 registers. The difference is not stored. The operands can be addressed
in a variety of modes. The most frequent use of CMP is to compare data or addresses preceding a conditional jump
instruction.
Table 5.21 lists the INC (increment) and DEC (decrement) instructions. The instructions for 80C51 microcontrollers
are supplemented by instructions that can address byte, word, and dword registers and increment or decrement them
by 1, 2, or 4 (denoted by #short). These instructions are supplied primarily for register–based address pointers and loop
counters.
The C251 Architecture provides the MUL (multiply) and DIV (divide) instructions for unsigned 8–bit and 16–bit data
(Table 5.22). Signed multiply and divide are left for the user to manage through a conversion process. The following
operations are implemented :
These instructions operate on pairs of byte registers (Rmd,Rms), word registers (WRjd,WRjs), or the accumulator and
B register (A, B). For 8–bit register multiplies, the result is stored in the word register that contains the first operand
register. For example, the product from an instruction MUL R3,R8 is stored in WR2. Similarly, for 16–bit multiplies,
the result is stored in the dword register that contains the first operand register. For example, the product from the
instruction MUL WR6,WR18 is stored in DR4.
For 8–bit divides, the operands are byte registers. The result is stored in the word register that contains the first operand
register. The quotient is stored in the lower byte, and the remainder is stored in the higher byte. A 16–bit divide is
similar. The first operand is a word register, and the result is stored in the double word register that contains that word
register. If the second operand (the divisor) is zero, the overflow flag (OV) is set and the other bits in PSW and PSW1
are meaningless.
4.8
as the contents of the accumulator, a byte register (Rn), or a word register (WRj)
in the instruction itself (immediate data)
in memory via direct or indirect addressing
eight–bit multiplication: 8 bits x 8 bits
sixteen–bit multiplication: 16 bits x 16 bits
eight–bit division: 8 bits / 8 bits
sixteen–bit division: 16 bits / 16 bits
16 bits (8–bit quotient, 8–bit remainder)
32 bits (16–bit quotient, 16–bit remainder)
16 bits
32 bits
Rev. C – May 7, 1999