TSC80251 TEMIC [TEMIC Semiconductors], TSC80251 Datasheet - Page 39

• Manufacturer Part Number: TSC80251
• Manufacturer: TEMIC [TEMIC Semiconductors]

TSC80251
4.6.5. Interrupt Processing
Interrupt processing is a dynamic operation that begins when a source requests an interrupt and lasts until the execution
of the first instruction in the interrupt service routine (See Figure 4.4. ). Response time is the amount of time between
the interrupt request and the resulting break in the current instruction stream. Latency is the amount of time between
the interrupt request and the execution of the first instruction in the interrupt service routine. These periods are dynamic
due to the presence of both fixed-time sequences and several variable conditions. These conditions contribute to total
elapsed time.
Both response time and latency begin with the request. The subsequent minimum fixed sequence comprises the
interrupt sample, poly, and request operations. The variables consist of (but are not limited to): specific instructions
in use at request time, internal versus external interrupt source requests, internal versus external program operation,
stack location, presence of wait states, page-mode operation and branch pointer length.
Note:
In the following discussion external interrupt request pins are assumed to be inactive for at least four state times prior to assertion. In this chapter
all external hardware signals maintain some setup period (i.e., less than one state time). Signals must meet V
state time under discussion. This setup state time is not included in examples or calculations for either response or latency.
4.6.6. Minimum Fixed Interrupt Time
All interrupts are sampled or polled every four state times (See Figure 4.4. ). One additional state time is required for
a context switch request. For code branches to jump locations in the current 64-Kbyte memory region (compatible with
80C51 microcontrollers), the context switch time is 11 states. Therefore, the minimum fixed poll and request time is
16 states (4 poll states + 1 request state + 11 states for the context switch = 16 state times).
Therefore, this minimum fixed period rests upon four assumptions:
4.14
Interrupt
External
Request
The source request is an internal interrupt with high enough priority to take precedence over other potential
interrupts.
The request is coincident with internal execution and needs no instruction completion time.
The program uses an internal stack location.
The ISR is in on-chip OTPROM/ROM.
Time
State
OSC
Response Time
Ending Instructions
Figure 4.4. Interrupt Process
Latency
PUSH PC
IH
and V
CALL ISR
IL
Rev. C – May 7, 1999
specifications prior to any
ISR