HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 31

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HT82A520R

Manufacturer Part Number
HT82A520R
Description
Full Speed USB 8-Bit OTP MCU with SPI
Manufacturer
HOLTEK [Holtek Semiconductor Inc]
Datasheet
system clock is stopped, then the WDT clock source will
also be stopped. Therefore the WDT will lose its protect-
ing purposes. In such cases the system cannot be re-
started by the WDT and can only be restarted using
external signals. For systems that operate in noisy envi-
ronments, using the internal WDT oscillator is therefore
the recommended choice.
Under normal program operation, a WDT time-out will in-
itialise a device reset and set the status bit TO. However,
if the system is in the Power Down Mode, when a WDT
time-out occurs, only the Program Counter and Stack
Pointer will be reset. Three methods can be adopted to
clear the contents of the WDT and the WDT prescaler.
The first is an external hardware reset, which means a
low level on the RES pin, the second is using the watch-
dog software instructions and the third is via a HALT in-
struction.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the sin-
gle CLR WDT instruction while the second is to use
the two commands CLR WDT1 and CLR WDT2 . For
the first option, a simple execution of CLR WDT will
clear the WDT while for the second option, both CLR
WDT1 and CLR WDT2 must both be executed to
successfully clear the WDT. Note that for this second
option, if CLR WDT1 is used to clear the WDT, succes-
sive executions of this instruction will have no effect,
only the execution of a CLR WDT2 instruction will
clear the WDT. Similarly, after the CLR WDT2 instruc-
tion has been executed, only a successive CLR WDT1
instruction can clear the Watchdog Timer.
Pulse Width Modulator
The device contains three Pulse Width Modulation
PWM outputs. Useful for such applications such as mo-
tor speed control, the PWM function provides an output
with a variable frequency, and with a duty cycle that can
be varied by setting particular values into the corre-
sponding register pair.
Rev.1.00
Channel
1
2
3
Mode
PWM
8+4
8+4
8+4
Output
PA4
PA5
PB0
Pin
PWM0DRH
PWM1DRH
PWM2DRH
PWM0DRL~
PWM1DRL~
PWM2DRL~
Register
Names
31
PWM Registers
Three register, located in the Data Memory are assigned
to each Pulse Width Modulator output and are known as
the PWM registers. It is in each register pair that the
12-bit value, which represents the overall duty cycle of
one modulation cycle of the output waveform, should be
placed. The PWM registers also contain the enable/dis-
able control bit for the PWM outputs. To increase the
PWM modulation frequency, each modulation cycle is
modulated into sixteen individual modulation
sub-sections, known as the 8+4 mode. Note that it is
only necessary to write the required modulation value
into the corresponding PWM register as the subdivision
of the waveform into its sub-modulation cycles is imple-
mented automatically within the microcontroller hard-
ware.
This method of dividing the original modulation cycle
into a further 16 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation fre-
quency should be understood.
As the PWM clock is defined by register PWMBR and
the system clock f
bit), and as the PWM value is 12-bits wide, the overall
PWM cycle frequency ( f
and the corresponding PWM modulation frequency for
8+4 mode is f
f
f
where PWMBRn=0~255 and f
12MHz , n=0~2 , according register whether it is PWM0,
PWM1 or PWM2
PWM
PWM
Modulation
Frequency
=
=
f
PWM
PWM
(1/f
(4/f
/256
SYS
SYS
)x(PWMBRn 1)
PWM
)x(PWMBRn 1)
HT82A520R/HT82A620R
SYS
1
/256 .
1
PWM Cycle
or f
Frequency
f
PWM
PWM
SYS
+
+
/4096
/4 (chosen via the PWM_S
) as the following equation
, when PWM_S=0
, when PWM_S=1
SYS
October 23, 2009
(PWM register
may be 6MHz,
PWM Cycle
value)/4096
Duty

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