HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 19

• Manufacturer Part Number: HT82A520R
• Description: Full Speed USB 8-Bit OTP MCU with SPI
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

To choose which of the three modes the Timer/Event
Counter is to operate in, either in the timer mode, the
event counting mode or the pulse width measurement
mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair TM1/TM0, must be set to the
required logic levels. The Timer/Event Counter on/off
bit, which is bit 4 of the Timer Control Register and
known as TON, provides the basic on/off control of the
Timer/Event Counter. Setting the bit high allows the
Timer/Event Counter to run, clearing the bit stops it run-
ning. If the Timer/Event Counter is in the event count or
pulse width measurement mode, the active transition
edge level type is selected by the logic level of bit 3 of
the Timer Control Register which is known as TE.
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal inter-
rupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair, TM1 or TM0, in the Timer Control Regis-
ter must be set to the correct value as shown.
In this mode the internal clock, f
ternal clock for the Timer/Event Counter. After the other
bits in the Timer Control Register have been setup, the
enable bit TON, which is bit 4 of the Timer Control Reg-
ister, can be set high to enable the Timer/Event Counter
to run. Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC0, is reset to zero.
Rev.1.00
Control Register Operating Mode
Select Bits for the Timer Mode
SYS
/4 is used as the in-
Event Counter Mode Timing Chart
Bit7 Bit6
Timer Mode Timing Chart
1
0
19
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, TM1/TM0, in
the Timer Control Register must be set to the correct
value as shown.
In this mode, the external timer pin, TMR, is used as the
Timer/Event Counter clock source, however it is not di-
vided by the internal prescaler. After the other bits in the
Timer Control Register have been setup, the enable bit
TON, which is bit 4 of the Timer Control Register, can be
set high to enable the Timer/Event Counter to run. If the
Active Edge Select bit TE, which is bit 3 of the Timer
Control Register, is low, the Timer/Event Counter will in-
crement each time the external timer pin receives a low
to high transition. If the Active Edge Select bit is high,
the counter will increment each time the external timer
pin receives a high to low transition. When it is full and
overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC0, is reset to zero.
As the external timer pin is an independent pin and not
shared with an I/O pin, the only thing to ensure the timer
operate as an event counter is to ensure that the Oper-
ating Mode Select bits in the Timer Control Register
place the Timer/Event Counter in the Event Counting
Mode. It should be noted that in the event counting
mode, even if the microcontroller is in the Power Down
Mode, the Timer/Event Counter will continue to record
externally changing logic events on the timer input pin.
As a result when the timer overflows it will generate a
timer interrupt and corresponding wake-up source.
Control Register Operating Mode
Select Bits for the Event Counter Mode
HT82A520R/HT82A620R
October 23, 2009
Bit7 Bit6
0
1