HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 24

• Manufacturer Part Number: HT82A520R
• Description: Full Speed USB 8-Bit OTP MCU with SPI
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
Suitable masking of the individual interrupts using the
interrupt registers can prevent simultaneous occur-
rences.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EMI, and external interrupt enable bit, EEI,
must first be set. An actual external interrupt will take
place when the external interrupt request flag, EIF is set,
a situation that will occur when a high to low transition
appears on the interrupt pins. The external interrupt pin
is pin-shared with the I/O pins PA6 can only be config-
ured as an external interrupt pin if the corresponding ex-
ternal interrupt enable bits in the interrupt control
register INTC0 have been set. The pins must also be
setup as inputs by setting the corresponding PAC.6 bits
in the port control register. When the interrupt is en-
abled, the stack is not full and a high to low transition ap-
pears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 08H will take
place. When the interrupt is serviced, the external inter-
rupt request flag, EIF will be automatically reset and the
EMI bit will be automatically cleared to disable other in-
terrupts. Note that any pull-high resistor configuration
options on these pins will remain valid even if the pins
are used as external interrupt inputs.
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ETI, must first be set. An actual
Timer/Event Counter interrupt will take place when the
Timer/Event Counter interrupt request flag, TF, is set, a
situation that will occur when the Timer/Event Counter
overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter overflow occurs, a
subroutine call to the timer interrupt vector at location
0CH , will take place. When the interrupt is serviced, the
timer interrupt request flag, TF, will be automatically re-
set and the EMI bit will be automatically cleared to dis-
able other interrupts.
Rev.1.00
USB Interrupt
External Interrupt
Timer/Event Counter Overflow
Interrupt
SPI Interrupt
Interrupt Source
Priority
1
2
3
4
000CH
Vector
0004H
0008H
0010H
24
SPI Interrupt
For a SPI Interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding SPI interrupt enable bit,
ESII must be first set. An actual SPI Interrupt will take
place when one of the two SPI interrupt request flags,
SIF is set, a situation that will occur when 8-bits of data
are transferred or received from either of the SPI inter-
faces. When the interrupt is enabled, the stack is not full
and an SPI interrupt occurs, a subroutine call to the SPI
interrupt vector at location 10H, will take place. When
the interrupt is serviced, the SPI interrupt request flag,
SIF will be automatically reset and the EMI bit will be au-
tomatically cleared to disable other interrupts.
USB Interrupt
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag, USBF, and the
EMI bit will be cleared to disable other interrupts.
When PC Host accesses the FIFO of the device, the
corresponding request USR bit is set, and a USB inter-
rupt is triggered. Therefore it can be determined which
FIFO has been accessed. When the interrupt has been
served, the corresponding bit should be cleared by the
program. When the device receive a USB Suspend sig-
nal from the Host PC, the suspend line, bit0 of USC, is
set and a USB interrupt is also triggered. Also when de-
vice receive a Resume signal from the Host PC, the re-
sume line, bit3 of USC, is set and a USB interrupt is
triggered.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt control register until the corre-
sponding interrupt is serviced or until the request flag is
cleared by a software instruction.
It is recommended that programs do not use the CALL
subroutine instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a CALL subroutine is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
A USB interrupts will be triggered by the following USB
events, at which point the the related interrupt request
Accessing the corresponding USB FIFO from the PC
A USB suspend signal from the PC
A USB resume signal from the PC
A USB Reset signal
flag, USBF in the INTC0 register, will be set.
HT82A520R/HT82A620R
October 23, 2009