HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 8

• Manufacturer Part Number: HT82A520R
• Description: Full Speed USB 8-Bit OTP MCU with SPI
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the inter-
nal system architecture. The range of devices take ad-
vantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It car-
ries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The inter-
nal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural fea-
tures ensure that a minimum of external components is
required to provide a functional I/O and A/D control sys-
tem with maximum reliability and flexibility.
Clocking and Pipelining
The main system clock, derived from a Crystal/Resona-
tor is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
functions. In this way, one T1~T4 clock cycle forms one
Rev.1.00
System Clocking and Pipelining
Instruction Fetching
8
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cy-
cles, the pipelining structure of the microcontroller en-
sures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute.
For instructions involving branches, such as jump or call
instructions, two instruction cycles are required to com-
plete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as JMP or CALL that demand a jump to a
non-consecutive Program Memory address. It must be
noted that only the lower 8 bits, known as the Program
Counter Low Register, are directly addressable by user.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
HT82A520R/HT82A620R
October 23, 2009