HT82A520R HOLTEK [Holtek Semiconductor Inc], HT82A520R Datasheet - Page 38

• Manufacturer Part Number: HT82A520R
• Description: Full Speed USB 8-Bit OTP MCU with SPI
• Manufacturer: HOLTEK [Holtek Semiconductor Inc]

SPI Serial Interface
The device includes one SPI Serial Interfaces. The SPI in-
terface is a full duplex serial data link, originally designed
by Motorola, which allows multiple devices connected to
the same SPI bus to communicate with each other. The
devices communicate using a master/slave technique
where only the single master device can initiate a data
transfer. A simple four line signal bus is used for all com-
munication.
SPI Interface Communication
Four lines are used for each function. These are, SDI -
Serial Data Input, SDO - Serial Data Output, SCK - Serial
Clock and SCS - Slave Select. Note that the condition of
the Slave Select line is conditioned by the CSEN bit in the
SBCR control register. If the CSEN bit is high then the
SCS line is active while if the bit is low then the SCS line
will be in a floating condition. The accompanying timing di-
agram depicts the basic timing protocol of the SPI bus.
SPI Registers
There are three registers for control of the SPI Interface.
These are the SBCR register which is the control register
and the SBDR which is the data register and SPIR register
which is the SPI mode control register. The SBCR register
is used to setup the required setup parameters for the SPI
bus and also used to store associated operating flags,
while the SBDR register is used for data storage.
The SPIR register is used to select SPI mode, clock polar-
ity edge selection and SPI enable or disable selection.
Rev.1.00
Ideal A/D Transfer Function
38
After Power on, the contents of the SBDR register will be
in an unknown condition while the SBCR register will de-
fault to the condition below:
Note that data written to the SBDR register will only be
written to the TXRX buffer, whereas data read from the
SBDR register will actual be read from the register.
SPI Bus Enable/Disable
To enable the SPI bus, the SBEN bit should be set high,
then wait for data to be written to the SBDR (TXRX buffer)
register. For the Master Mode, after data has been written
to the SBDR (TXRX buffer) register then transmission or
reception will start automatically. When all the data has
been transferred, the TRF bit should be set. For the Slave
Mode, when clock pulses are received on SCK, data in the
TXRX buffer will be shifted out or data on SDI will be
shifted in.
To Disable the SPI bus SCK, SDI, SDO, SCS should be
I/O mode.
CKS
0
M1
1
M0
1
SBEN
HT82A520R/HT82A620R
0
MLS
0
CSEN
0
October 23, 2009
WCOL
0
TRF
0