HD6412350 Hitachi, HD6412350 Datasheet - Page 638

• Manufacturer Part Number: HD6412350
• Description: (HD6412350 / HD6432351) 16-BIT MICROCONTROLLER
• Manufacturer: Hitachi

Thus the reception margin in asynchronous mode is given by the following formula.
M = (0.5 –
Where M: Reception margin (%)
Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as
follows.
When D = 0.5 and F = 0,
Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and
transmit mode as described below.
[1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically
[2] The RDRF bit in SSR is not set for a frame in which an error has occurred.
[3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
[4] If no error is found when the received parity bit is checked, the receive operation is judged to
[5] When a normal frame is received, the pin retains the high-impedance state at the timing for
618
Retransfer operation when SCI is in receive mode
Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode.
set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The
PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE
bit in SCR is enabled at this time, an RXI interrupt request is generated.
If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read
automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is
automatically cleared to 0.
error signal transmission.
M = (0.5 – 1/2 372) 100%
N: Ratio of bit rate to clock (N = 372)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
= 49.866%
2N
1
) – (L – 0.5) F –
D – 0.5
N
(1 + F
100%