PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 21

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

2 0 Configuration Registers
2 4 INDEX AND DATA REGISTERS
Another general aspect of the Configuration Registers is
that the Index and the Data Register pair can be relocated
to one of four locations This is controlled through a hard-
ware strapping option on pins (BADDR0 1) and it allows the
registers to avoid conflicts with other adapters in the I O
address space Table 2-2 shows the address options
2 5 BASE CONFIGURATION REGISTERS
2 5 1 Function Enable Register (FER Index 00h)
This register enables and disables major chip functions (e g
UARTs parallel ports FDC etc ) Disabled functions have
their clocks automatically powered-down but the data in
their registers remains intact It also selects whether the
FDC and the IDE controller is located at their primary or
secondary address
Bit 0 When this bit is 1 the parallel port can be accessed at
Bit 1 When this bit is 1 UART1 can be accessed at the
BADDR1
0
0
1
1
the address specified in the FAR
address specified in the FAR When this bit is 0 ac-
cess to UART1 is blocked and it is in power-down
mode The UART1 registers retain all data in power-
down mode
Caution Any UART1 interrupt that is enabled and
active or becomes active after UART1 is disabled
asserts the associated IRQ pin If disabling UART1
via software clear the IRQ Enable bit (MCR3) to 0
before clearing FER 1 This is not an issue after reset
because MCR3 is 0 until it is written
TABLE 2-2 Index and Data Register
BADDR0
Optional Locations
0
1
0
1
Index Addr
26E
15C
FIGURE 2-2 PC87332 Four Floppy Drive Circuit Example
398
2E
Data Addr
(Continued)
15D
399
26F
2F
21
Bit 2 When this bit is 1 UART2 can be accessed at the
Bit 3 When this bit is 1 the FDC can be accessed at the
Bit 4 When this bit is 0 the PC87332 can control two floppy
Bit 5 This bit selects the primary or secondary FDC ad-
Bit 6 When this bit is a 1 the IDE drive interface can be
Bit 7 This bit selects the primary or secondary IDE ad-
address specified in the FAR When this bit is 0 ac-
cess to UART2 is blocked and it is in power-down
mode The UART2 registers retain all data in power-
down mode
Caution Any UART2 interrupt that is enabled and
active or becomes active after UART2 is disabled as-
serts the associated IRQ pin If disabling UART2 via
software clear the IRQ Enable bit (MCR3) to 0 be-
fore clearing FER 1 This is not an issue after reset
because MCR3 is 0 until it is written
address specified in the FER bits When this bit is 0
access to the FDC is blocked and it is in power-down
mode The FDC registers retain all data in power-
down mode
disk drives directly without an external decoder
When this bit is 1 the two drive select signals and two
motor enable signals from the FDC are encoded so
that four floppy disk drives can be controlled (see
Table 2-3 and Figure 2-2 ) Controlling four FDDs re-
quires an external decoder The pin states shown in
Table 2-3 are a direct result of the bit patterns shown
All other bit patterns produce pin states that should
not be decoded to enable any drive or motor
dress (See Table 2-4 )
accessed at the address specified by FER bit 7
When it is 0 access to the IDE interface is blocked
the IDE control signals (i e HCS0 HCS1 IDELO
IDEHI) are held in the inactive state and the IDED7
signal is in TRI-STATE
dress (See Table 2-4 )
TL C 11930 – 5