PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 32

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

3 0 FDC Register Description
The Mode command can also disable the FIFO for either
reads or writes separately The FIFO allows the system a
larger latency without causing a disk overrun underrun er-
ror The FIFO is typically utilized with multitasking operating
systems and or when running systems at or above a
1 Mbps data rate In its default state the FIFO is disabled
and contains a zero threshold The default state is entered
after a hardware reset
Data Register (FIFO)
During the Execution Phase of a command involving a data
transfer to from the FIFO the system must respond
to a data transfer service request based on the following
formula
This formula is good for all data rates with the FIFO enabled
or disabled THRESH is a four bit value programmed in the
Configure command which sets the FIFO threshold If the
FIFO is disabled THRESH is zero in the above formula The
last term of the formula (16
to the microcode overhead required by the FDC This delay
is also data rate dependent See Table 9-1 for the t
t
t
The programmable FIFO threshold (THRESH) is useful in
adjusting the floppy controller to the speed of the system In
other words a slow system with a sluggish DMA transfer
capability uses a high value of THRESH giving the system
more time to respond to a data transfer service request
(DRQ for DMA mode or IRQ6 for Interrupt mode) Converse-
ly a fast system with quick response to a data transfer serv-
ice request uses a low value of THRESH
3 1 8 Digital Input Register (DIR)
This diagnostic register is used to detect the state of the
DSKCHG disk interface input and some diagnostic signals
The function of this register depends on its mode of opera-
tion When in the PC-AT mode the D6–0 are TRI-STATE to
avoid conflict with the fixed disk status register at the same
address DIR is unaffected by a software reset
DIR PC-AT Mode
D7
D6–0
ICP
ICP
DESC
RESET
COND
DESC
RESET
COND
Maximum Allowable Data Transfer Service Time
times See Section 9 3 2 for a description of t
Disk Changed Active high status of DSKCHG disk
interface input During power-down this bit is invalid
if it is read by the software
Unused by the FDC (at TRI-STATE) The bits are
used by the Hard Disk Controller Status Register
(THRESH
DSKCHG
D7
N A
D7
D6
a
N A
D6
X
1)
D5
c
N A
D5
X
8
c
c
D4
Byte Mode
Data 7 0
t
ICP
N A
t
D4
DRP
X
) is an inherent delay due
D3
N A
b
D3
X
(16
D2
N A
D2
X
c
t
ICP
Read Only
(Continued)
D1
N A
D1
X
)
DRP
DRP
N A
D0
D0
and
and
X
32
DIR PS 2 Mode
D7
D6– 3
D2– 1
D0
DIR Model 30 Mode
D7
D6– 4
D3
D2
D1– 0
3 1 9 Configuration Control Register (CCR)
This is the write-only data rate register commonly used in
PC-AT applications This register is not affected by a soft-
ware reset and is set to 250 kbps after a hardware reset
The data rate of the floppy controller is determined by the
last write to either the CCR or DSR
CCR PC-AT and PS 2 Modes
D7–2
D1– 0
DESC
RESET
COND
DESC
RESET
COND
DESC
RESET
COND
DSKCHG
Disk Changed Active high status of DSKCHG disk
interface input During power-down this bit is invalid
if it is read by the software
Reserved Always 1
Data Rate Select 1 0 These bits indicate the
status of the DRATE1 – 0 bits programmed through
the DSR or CCR
High Density This bit is low when the 1 Mbps
2 Mbps or 500 kbps data rate is chosen and high
when the 300 kbps or 250 kbps data rate is chosen
This bit is independent of the IDENT value
Disk Changed Active low status of DSKCHG disk
interface input During power-down this bit is invalid
if it is read by the software
Reserved Always 0
DMA Enable Active high status of the DMAEN bit
in the DOR
No Precompensation Active high status of the
NOPRE bit in the CCR
Data Rate Select 1 0 These bits indicate the
status of the DRATE 1– 0 bits programmed through
the DSR or CCR
Reserved Should be set to 0
Data Rate Select 1 0 These bits determine the
data rate of the floppy controller See Table 3-7 for
the appropriate values
DSKCHG
N A
D7
N A
N A
0
D7
D7
N A
D6
0
D6 D5 D4
N A N A N A N A
0
0
D6
1
N A
D5
0
0
0
D5
1
0
0
N A
D4
0
D4
DMAEN NOPRE DRATE1 DRATE0
1
D3
0
N A
D3
0
D3
1
N A
DRATE1 DRATE0
D2
D2
0
0
N A
D2
DRATE1
D1
1
D1
1
N A
D1
Write Only
DRATE0
D0
HIGH
D0
0
DEN
0
D0
1