PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 71

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

7 0 Parallel Port
Bit 3 This bit represents the current state of the printer
Bit 4 This bit represents the current state of the printer
Bit 5 This bit represents the current state of the printer
Bit 6 This bit represents the current state of the printer
Bit 7 This bit represents the current state of the printer
7 4 CONTROL REGISTER (CTR)
This register provides all output signals to control the print-
er Except for bit 5 it is a read and write register
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
In the Extended mode if CTR4
latched low when the ACK signal makes a transition
from low to high
Reading this bit sets it to a 1
error signal (ERROR) The printer sets this bit low
when there is a printer error This bit follows the state
of the ERR pin
select signal (SLCT) The printer sets this bit high
when it is selected This bit follows the state of the
SLCT pin
paper end signal (PE) The printer sets this bit high
when it detects the end of the paper This bit follows
the state of the PE pin
acknowledge signal (ACK) The printer pulses this
signal low after it has received a character and is
ready to receive another one This bit follows the
state of the ACK pin
busy signal (BUSY) The printer sets this bit low when
it is busy and cannot accept another character This
bit is the inverse of the (BUSY WAIT) pin
This bit (STB) directly controls the data strobe sig-
nal to the printer via the STB pin This bit is the
inverse of the STB pin
This bit (AFD) directly controls the automatic feed
XT signal to the printer via the AFD pin Setting this
bit high causes the printer to automatically feed
after each line is printed This bit is the inverse of
the AFD pin
This bit (INIT) directly controls the signal to initial-
ize the printer via the INIT pin Setting this bit to
low initializes the printer This bit follows the INIT
pin
Note This bit must be set to 1 before enabling the EPP or ECP
This bit directly controls the select-in (SLIN) signal
to the printer via the SLIN pin Setting this bit high
selects the printer It is the inverse of the SLIN pin
This bit controls the interrupt generated by the
ACK signal Its function changes slightly depend-
ing on the parallel port mode selected In ECP
mode this bit should be set to 0 In the following
description IRQx indicates either IRQ5 or IRQ7
(based upon PTR3)
modes via bits 0 or 2 of the PCR register
(Continued)
e
1 then this bit is
TL C 11930 – 14
71
Bit 5
Bits 6 7 Reserved These bits are always 1
Normally when the Control Register is read the bit values
are provided by the internal output data latch These bit
values can be superseded by the logic level of the STB
AFD INIT and SLIN pins if these pins are forced high or low
by an external voltage In order to force these pins high or
low the corresponding bits should be set to their inactive
state (e g AFD
7-4
7 5 ENHANCED PARALLEL PORT OPERATION
EPP mode provides for greater throughput and more com-
plexity than the Compatible or Extended modes by support-
ing faster transfer times and a mechanism that allows the
host to address peripheral device registers directly Faster
transfers are achieved by automatically generating the ad-
dress and data strobes EPP is compatible with both Com-
patible and Extended mode parallel-port devices It consists
of eight (0– 7) single-byte registers (See Table 7-5 )
There are two EPP modes
EPP rev 1 7 is supported when bit 0 of PCR is 1 and bit 1 of
PCR is 0
EPP rev 1 9 (IEEE 1284) is supported when bit 0 of PCR is
1 and bit 1 of PCR is 1
EPP is supported for a parallel port whose base address is
278h or 378h but not for a parallel port whose base ad-
dress is 3BCh (there are no EPP registers at 3BFh) There
are four EPP transfer operations address write address
read data write and data read An EPP transfer operation is
composed of a host read or write cycle (from or to an EPP
register) and an EPP read or write cycle (from a peripheral
device to an EPP register or from an EPP register to a
peripheral device)
SLIN
INIT
AFD
STB
IRQ5 7
Signal
Compatible mode
when bit 4
when bit 4
Extended mode
when bit 4
when bit 4
EPP mode
when bit 4
when bit 4
This bit determines the parallel port direction when
bit 7 of PTR is 1 The default condition results in
the parallel port being in the output mode This is a
Read Write bit in EPP mode In SPP mode it is a
write only bit a read from it will return 1 See
Table 7-3 for further details
TABLE 7-4 Parallel Port Reset States
e
Reset Control
STB
e
e
e
e
e
e
MR
MR
MR
MR
MR
0 IRQx is floated
1 IRQx follows ACK transitions
0 IRQx is floated
1 IRQx becomes active on ACK trail-
ing edge
0 IRQx is floated
1 IRQx is pulsed when ACK is acti-
vated or an EPP timeout occurs
e
SLIN
e
0 INIT
State after Reset
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
e
Zero
1) See Table