PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 79

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

7 0 Parallel Port
7 9 AUTOMATIC DATA TRANSFER (Modes 010 and 011)
Automatic data transfer (ECP cycles generated by hard-
ware) is supported only in modes 010 and 011 Automatic
DMA access to fill or empty the FIFO is supported in modes
010 011 and 110 Mode 010 is for the forward direction
only The direction bit is forced to 0 and PD0–7 is driven
Mode 011 is for both the forward and backward directions
The direction bit controls whether PD0–7 is driven
Automatic Run Length Expanding (RLE) is supported in the
backward direction
Note 1 FIFO-full condition is checked before every expanded byte push
Note 2 A pending DMA request is removed and a pending RLE expansion
Note 3 The two FIFO ports are neither synchronized nor linked together
Note 4 In the forward direction the empty bit is updated when the ECP
Note 5 ZWS is not asserted for DMA cycles
Note 6 The one-bit command data tag is used only in forward direction
7 9 1 Forward Direction (Bit 5 of DCR
When the ECP is in forward direction and the FIFO is not full
(bit 1 of ECR is 0) the FIFO can be filled by software writes
to the FIFO registers (AFIFO and DFIFO in mode 011 and
CFIFO in mode 010)
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to fill the
FIFO with normal data bytes
When the ECP is in forward direction and the FIFO is not
empty (bit 0 of ECR is 0) the ECP pops a byte from the FIFO
and issues a write cycle to the peripheral device The ECP
drives AFD according to the operation mode (ECR bits 5 –7)
and according to the tag of the popped byte as follows In
Parallel Port FIFO mode (mode 010) AFD is controlled by bit
1 of DCR In ECP mode (mode 011) AFD is controlled by the
popped tag AFD is driven high for normal data bytes and
driven low for command bytes
7 9 2 ECP Forward Write Cycle
An ECP write cycle starts when the ECP drives the popped
tag onto AFD and the popped byte onto PD0–7 When
BUSY is low the ECP asserts STB In 010 mode the ECP
deasserts STB to terminate the write cycle In 011 mode the
ECP waits for BUSY to be high
When BUSY is high the ECP deasserts STB When BUSY is
changed to low it changes AFD and PD0–7
is aborted when switching from modes 010 or 011 to other modes
except via the empty and full FIFO status bits The FIFO shall not
delay the push and pop operations even when they are performed
concurrently Care must be taken not to corrupt PD0–7 or D0–7
while the other FIFO port is accessed
cycle is completed not right after the last byte is popped out of the
FIFO (valid cleared on cycle end)
FIGURE 7-6 ECP Forward Write Cycle
(Continued)
e
0)
TL C 11930 – 20
79
7 9 3 Backward Direction (Bit 5 of DCR is 1)
When the ECP is in the backward direction and the FIFO is
not full (bit 1 of ECR is 0) the ECP issues a read cycle from
the peripheral device and monitors the BUSY signal If
BUSY is high the byte is a data byte and it is pushed into the
FIFO If BUSY is low the byte is a command byte The ECP
checks bit 7 of the command byte if it is high the byte is
ignored if it is low the byte is tagged as an RLC byte (not
pushed into the FIFO but used as a Run Length Count to
expand the next byte read) Following an RLC read the ECP
issues a read cycle from the peripheral device to read the
data byte to be expanded This byte is considered a data
byte regardless of its BUSY state (even if it is low) This
byte is pushed into the FIFO (RLC
push the byte once RLC
When the ECP is in the backward direction and the FIFO is
not empty (bit 0 of ECR is 0) the FIFO can be emptied by
software reads from the FIFO register (only DFIFO in mode
011 no AFIFO and CFIFO read)
When DMA is enabled (bit 3 of ECR is 1 and bit 2 of ECR is
0) the ECP automatically issues DMA requests to empty the
FIFO (only in mode 011)
7 9 4 ECP Backward Read Cycle
An ECP read cycle starts when the ECP drives AFD low
The peripheral device drives BUSY high for a normal data
read cycle or drives BUSY low for a command read cycle
and drives the byte to be read onto PD0– 7
When ACK is asserted the ECP drives AFD high When AFD
is high the peripheral device deasserts ACK The ECP reads
the PD0– 7 byte then drives AFD low When AFD is low the
peripheral device may change BUSY and PD0– 7 states in
preparation for the next cycle
7 10 FIFO TEST ACCESS (Mode 110)
Mode 110 is used for testing the FIFO in PIO and DMA
cycles Both read and write operations (pop and push) are
supported regardless of the direction bit
In the forward direction PD0– 7 are driven but the data is
undefined This mode can be used to measure the host-
ECP cycle throughput usually with DMA cycles This mode
can also be used to check the FIFO depth and its interrupt
threshold usually with PIO cycles
FIGURE 7-7 ECP Backward Read Cycle
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127 push the byte 128 times)
a
1) times (i e RLC
TL C 11930 – 21
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0