PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 66

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

6 0 Serial Ports
Note 1 Boldface bits are permanently low
Note 2 Bits 7–4 are driven by the input signals
6 3 PROGRAMMABLE BAUD RATE GENERATOR
The PC87332 contains two independently programmable
Baud rate Generators The 24 MHz crystal oscillator fre-
quency input is divided by 13 resulting in a frequency of
1 8462 MHz This is sent to each Baud rate Generator and
divided by the divisor of the associated UART The output
frequency of the Baud rate Generator (BOUT1 2) is 16
the baud rate
The output of each Baud rate Generator drives the transmit-
ter and receiver sections of the associated serial channel
Two 8-bit latches per channel store the divisor in a 16-bit
binary format These Divisor Latches must be loaded during
initialization to ensure proper operation of the Baud rate
Generator Upon loading either of the Divisor Latches a
16-bit Baud Counter is loaded Table 6-4 provides decimal
divisors to use with crystal frequencies of 24 MHz The os-
cillator input to the chip should always be 24 MHz to ensure
that the Floppy Disk Controller timing is accurate and that
the UART divisors are compatible with existing software
Using a divisor of zero is not recommended
Interrupt Enable
Interrupt Identification
FIFO Control
Line Control
MODEM Control
Line Status
MODEM Status
SOUT
INTR (RCVR Errors)
INTR (RCVR Data Ready)
INTR (THRE)
INTR (Modem Status Changes)
Interrupt Enable Bit
RTS
DTR
RCVR FIFO
XMIT FIFO
divisor
Register or Signal
e
(frequency input) (baud rate
(Continued)
TABLE 6-3 PC87332 UART Reset Configuration
Master Reset (MR)
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Master Reset
Read LSR MR
Read RBR MR
Read IIR Write THR MR
Read MSR MR
Master Reset
Master Reset
Master Reset
MR or (FCR1
MR or (FCR2
c
16)
e
e
c
1 and FCR0
1 and FCR0
Reset Control
66
Note The percent error for all baud rates except where indicated other-
e
e
Baud Rate
115200
wise is 0 2%
1) or Change in FCR0
1) or Change in FCR0
19200
38400
57600
1200
1800
2000
2400
3600
4800
7200
9600
110
134 5
150
300
600
50
75
TABLE 6-4 PC87332 UART Divisors
24 MHz Input Divided to 1 8462 MHz
Baud Rates and Clock Frequencies
Decimal Divisor
for 16 x Clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
0000 0000 (Note 1)
0000 0001
0000 0000
0000 0000
0000 0000
0110 0000
XXXX 0000 (Note 2)
High
Low TRI-STATE
Low TRI-STATE
Low Low TRI-STATE
Low TRI-STATE
Low
High
High
All Bits Low
All Bits Low
Reset State
Error (Note)
Percent
0 1
0 4
0 5