PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 38

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

4 0 FDC Command Set Description
4 1 4 Invalid Command
If an invalid command (illegal Opcode byte in the Command
Phase) is received by the controller the controller responds
with ST0 in the Result Phase The controller does not gen-
erate an interrupt during this condition Bits 6 and 7 in the
MSR are both set to a 1 indicating to the P that the con-
troller is in the Result Phase and the contents of ST0 must
be read The system reads an 80h value from ST0 indicating
an invalid command was received
Command Phase
Execution Phase None
Result Phase
4 1 5 Lock Command
The Lock command allows the user full control of the FIFO
parameters after a software reset If the LOCK bit is set to 1
then the FIFO THRESH and PRETRK bits in the Configure
command are not affected by a software reset In addition
the FWR FRD and BST bits in the Mode command are
unaffected by a software reset If the LOCK is 0 (default
after a hardware reset) then the above bits are set to their
default values after a software reset This command is use-
ful if the system designer wishes to keep the FIFO enabled
and retain the other FIFO parameter values (such as
THRESH) after a software reset
After the command byte is written the result byte must be
read before continuing to the next command The execution
of the Lock command is not performed until the result byte
is read by the P If the part is reset after the command byte
is written but before the result byte is read then the Lock
command execution is not performed This is done to pre-
vent accidental execution of the Lock command
Command Phase
Execution Phase Internal Lock register is written
Result Phase
4 1 6 Mode Command
This command is used to select the special features of the
controller The bits for the Command Phase bytes are
shown in Section 4 1 Command Set Summary and their
function is described below These bits are set to their de-
fault values after a hardware reset The default value of
each bit is denoted by a ‘‘bullet’’ to the left of each item The
value of each parameter after a software reset is explained
Command Phase
Execution Phase Internal registers are written
Result Phase None
TMR
FWR
LOCK
0
0
0
DENSEL
0
FRD
IAF
0
0
0
0
BST
BFR
IPS
0
0
Status Register 0 (80h)
0
Invalid Op Codes
LOCK
R255
WLD
0
0
0
1
0
0
0
LOW PWR
0
0
Head Settle
1
0
RG
0
0
0
0
0
1
0
0
ETR
PU
1
0
0
0
(Continued)
38
TMR Motor Timer mode Default after a software reset
IAF Index Address Format Default after a software reset
IPS Implied Seek Default after a software reset
LOW
PWR Low Power mode Default after a software reset
ETR Extended Track Range Default after a software re-
FWR FIFO Write Disable for P write transfers to control-
0
0
1
1
0
00
set
1
0
01
10
11
1
ler Default after a software reset if LOCK is 0 If
LOCK is 1 FWR retains its value after a software
reset
Note This bit is only valid if the FIFO is enabled in the Configure
0
1
e
e
e
e
e
e
e
e
e
e
e
e
e
e
The implied seek bit in the command byte of a
read write scan or verify is ignored Implied
seeks could still be enabled by the EIS bit in the
Configure command
The controller formats tracks with the Index Ad-
dress Field included (IBM and Perpendicular for-
mat )
The IPS bit in the command byte of a read write
scan or verify is enabled so that if it is set the
controller performs seek and sense interrupt op-
erations before executing the command
The controller formats tracks without including
the Index Address Field (ISO format )
Track number is stored as a standard 8-bit value
compatible with the IBM ISO and Perpendicular
formats This allows access of up to 256 tracks
during a seek operation
Track number is stored as a 12-bit value The
upper four bits of the track value are stored in
the upper four bits of the head number in the
sector Address Field This allows access of up to
4096 tracks during a seek operation With this bit
set an extra byte is required in the Seek Com-
mand Phase and Sense Interrupt Result Phase
Timers for motor on and motor off are defined
for Mode 1 (See Specify command )
Timers for motor on and motor off are defined
for Mode 2 (See Specify command )
Enable FIFO
cution Phase use the internal FIFO
Disable FIFO All write data transfers take place
without the FIFO
command If the FIFO is not enabled in the Configure com-
mand then this bit is a don’t care
Completely disable the low power mode
Automatic low power For 500 kbps operation
go into low power mode 512 ms after the head
unload timer times out For 250 kbps operation
the timeout period is doubled to 1s
Manual low power Go into low power mode
now
Not used
P write transfers druing the Exe-