PC87332VLJ-5 NSC [National Semiconductor], PC87332VLJ-5 Datasheet - Page 70

• Manufacturer Part Number: PC87332VLJ-5
• Description: PC87332VLJ (3.3V/5V) and PC87332VLJ-5 (5V) (SuperI/OTM III Premium Green) Floppy Disk Controller, Dual UARTs, IEEE1284 Parallel Port, and IDE Interfac
• Manufacturer: NSC [National Semiconductor]

7 0 Parallel Port
7 1 INTRODUCTION
This parallel interface is designed to provide all of the sig-
nals and registers needed to communicate through a stan-
dard parallel printer port as found in the IBM PC-XT PC-AT
PS 2 and Centronics systems This parallel port supports
three standard modes of operation SPP EPP ECP The
Standard Parallel Port (SPP) is a software based protocol
with performance of up to 150 kbps
The Enhanced Parallel Port (EPP) is a hardware protocol
which offers up to 2 Mbps
The Extended Capabilities Port (ECP) is also a hardware
protocol with up to 2 Mbps transfer rate In addition the
ECP has FIFO’s for receive and transmit and DMA support
to reduce the CPU overhead The ECP mode 0 is in fact
compatible with the SPP mode The ECP specification de-
fines the AC DC parameters of the signals to allow fast
communication without termination problems
All the above standards are incorporated into the 1284 IEEE
specifications
The address decoding of the registers utilizing A0 and A1 is
shown in Table 7-1 Table 7-3 shows the Reset states of
Parallel port registers and pin signals These registers are
shown in Section 7 2 to Section 7 4
Special circuitry provides protection against damage that
might be caused when the printer is powered but the
PC87332 is not
There are two Standard Parallel Port (SPP) modes of opera-
tion (Compatible and Extended see Table 7-2) two En-
hanced Parallel Port (EPP) modes of operation and one Ex-
tended Capabilities Port (ECP) mode to complete a full IEEE
1284 parallel port
In Compatible mode a write operation causes the data to be
presented on pins PD0–7 A read operation in this mode
causes the Data Register to present the last data written to
it by the CPU See Table 7-3
In the Extended mode a write operation to the data register
causes the data to be latched If the Data Port Direction bit
(Control Register (CTR) bit 5) is 0 the latched data is pre-
sented to the pins and a read operation from this register
allows the CPU to read the last data it wrote to the port If
CTR5 is 1 the data is only latched and a read from this
register causes the port to present the data on pins PD0–7
See Table 7-2
A1
TABLE 7-2 Standard Parallel Port Modes Selection
0
0
1
1
TABLE 7-1 Parallel Interface Register Addresses
A0
Port Function
Compatible
Extended
0
1
0
1
Address
0
1
2
3
Data
Status
Control
TRI-STATE
Register
PTR7
Read Write
Read
Read Write
0
1
Access
70
7 2 DATA REGISTER (DTR)
This is a bidirectional data port that transfers 8-bit data The
direction is determined by the Power and Test Configuration
Register (PTR) bit 7 and the CTR5 bits When PTR7 is high
the CTR5 bit will determine the data direction in conjunction
with the Read and Write strobes When PTR7 bit is low the
parallel port operates in the output mode only The reset
value of this register is 0 See Table 7-3
7 3 STATUS REGISTER (STR)
This register provides status for the TIMEOUT ERROR
SLCT PE ACK and BUSY signals for a connected printer
It is a read only register Writing to it is an invalid operation
that has no effect
Bit 0 When in EPP mode this is the timeout status bit
Bit 1 Reserved this bit is always 1
Bit 2 In the compatible mode (PTR7 bit is 0) or in ECP and
PTR7
TABLE 7-3 SPP Data Register Read and Write Modes
0
0
1
1
1
1
When this bit is 0 no timeout
When this bit is 1 timeout occurred on EPP cycle
(minimum 10
read i e consecutive reads (after the first read) al-
ways return 0 It is also cleared to 0 when EPP is
enabled (bit 0 of PCR is changed from 0 to 1)
When not in EPP mode this bit is 1
EPP mode with bit 4 of PCR
one
In the Extended Mode (PTR7 bit is 1) or in ECP and
EPP with bit 4 of PCR
bit
CTR5
X
X
0
1
0
1
RD
1
0
1
1
0
0
sec) It is cleared to 0 after STR is
WR
0
1
0
0
1
1
e
Data Written to PD0– 7
Data Read from the Output
Latch
Data Written to PD0– 7
Data Written is Latched
Data Read from the Output
Latch
Data Read from PD0– 7
1 this bit is the IRQ Status
e
0 this bit is always
Result
TL C 11930 – 12
TL C 11930 – 13